Simulation Results: adc_ctrl

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 70.76 %
  • code
  • 96.76 %
  • assert
  • 96.92 %
  • func
  • 18.61 %
  • line
  • 99.02 %
  • branch
  • 98.39 %
  • cond
  • 94.50 %
  • toggle
  • 100.00 %
  • FSM
  • 91.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 11.720s 5750.045us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.360s 764.987us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.030s 382.106us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 40.860s 27111.073us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 3.130s 1192.879us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 2.350s 454.870us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.030s 382.106us 1 1 100.00
adc_ctrl_csr_aliasing 3.130s 1192.879us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 64.530s 33742.806us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 56.610s 54225.720us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 39.030s 19873.828us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 24.320s 18997.381us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 9.490s 21639.294us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 37.240s 64140.244us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 20.380s 19261.014us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 20.850s 19574.594us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 8.660s 3320.804us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 18.010s 44885.936us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 281.250s 129678.875us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 273.210s 109693.526us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.090s 371.049us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.150s 521.862us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.790s 646.058us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.790s 646.058us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.360s 764.987us 1 1 100.00
adc_ctrl_csr_rw 1.030s 382.106us 1 1 100.00
adc_ctrl_csr_aliasing 3.130s 1192.879us 1 1 100.00
adc_ctrl_same_csr_outstanding 11.780s 4786.278us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.360s 764.987us 1 1 100.00
adc_ctrl_csr_rw 1.030s 382.106us 1 1 100.00
adc_ctrl_csr_aliasing 3.130s 1192.879us 1 1 100.00
adc_ctrl_same_csr_outstanding 11.780s 4786.278us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 8.110s 4438.016us 1 1 100.00
adc_ctrl_tl_intg_err 3.140s 4249.153us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 3.140s 4249.153us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 9.550s 27040.328us 1 1 100.00