Simulation Results: aes/masked

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.76 %
  • code
  • 93.58 %
  • assert
  • 97.94 %
  • func
  • 74.76 %
  • block
  • 94.22 %
  • line
  • 95.89 %
  • branch
  • 87.09 %
  • toggle
  • 97.99 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 220.688us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 77.653us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 93.495us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 128.165us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 472.564us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 149.645us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 3.000s 130.960us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 128.165us 1 1 100.00
aes_csr_aliasing 2.000s 149.645us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 77.653us 1 1 100.00
aes_config_error 4.000s 137.886us 1 1 100.00
aes_stress 4.000s 433.295us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 77.653us 1 1 100.00
aes_config_error 4.000s 137.886us 1 1 100.00
aes_stress 4.000s 433.295us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 433.295us 1 1 100.00
aes_b2b 15.000s 1259.250us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 433.295us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 3.000s 77.653us 1 1 100.00
aes_config_error 4.000s 137.886us 1 1 100.00
aes_stress 4.000s 433.295us 1 1 100.00
aes_alert_reset 1.000s 8.067us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 102.488us 1 1 100.00
aes_config_error 4.000s 137.886us 1 1 100.00
aes_alert_reset 1.000s 8.067us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 117.871us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 10.000s 878.075us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 1.000s 8.067us 0 1 0.00
stress 1 1 100.00
aes_stress 4.000s 433.295us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 433.295us 1 1 100.00
aes_sideload 2.000s 123.323us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 392.322us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 36.000s 839.772us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 168.047us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 61.850us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 61.850us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 93.495us 1 1 100.00
aes_csr_rw 2.000s 128.165us 1 1 100.00
aes_csr_aliasing 2.000s 149.645us 1 1 100.00
aes_same_csr_outstanding 2.000s 205.368us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 93.495us 1 1 100.00
aes_csr_rw 2.000s 128.165us 1 1 100.00
aes_csr_aliasing 2.000s 149.645us 1 1 100.00
aes_same_csr_outstanding 2.000s 205.368us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 147.153us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 6.000s 176.726us 0 1 0.00
aes_control_fi 2.000s 127.605us 1 1 100.00
aes_cipher_fi 3.000s 130.533us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 158.291us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 158.291us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 158.291us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 158.291us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 231.783us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 817.403us 1 1 100.00
aes_tl_intg_err 3.000s 187.180us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 187.180us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 1.000s 8.067us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 158.291us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 158.291us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 77.653us 1 1 100.00
aes_stress 4.000s 433.295us 1 1 100.00
aes_alert_reset 1.000s 8.067us 0 1 0.00
aes_core_fi 4.000s 205.467us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 4.000s 137.886us 1 1 100.00
aes_stress 4.000s 433.295us 1 1 100.00
aes_core_fi 4.000s 205.467us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 158.291us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 113.758us 1 1 100.00
aes_stress 4.000s 433.295us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 433.295us 1 1 100.00
aes_sideload 2.000s 123.323us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 113.758us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 113.758us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 113.758us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 113.758us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 113.758us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 433.295us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 433.295us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 6.000s 176.726us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 6.000s 176.726us 0 1 0.00
aes_control_fi 2.000s 127.605us 1 1 100.00
aes_cipher_fi 3.000s 130.533us 1 1 100.00
aes_ctr_fi 2.000s 84.324us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 6.000s 176.726us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 6.000s 176.726us 0 1 0.00
aes_control_fi 2.000s 127.605us 1 1 100.00
aes_cipher_fi 3.000s 130.533us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 130.533us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 6.000s 176.726us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 6.000s 176.726us 0 1 0.00
aes_control_fi 2.000s 127.605us 1 1 100.00
aes_ctr_fi 2.000s 84.324us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 6.000s 176.726us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 6.000s 176.726us 0 1 0.00
aes_control_fi 2.000s 127.605us 1 1 100.00
aes_cipher_fi 3.000s 130.533us 1 1 100.00
aes_ctr_fi 2.000s 84.324us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 1.000s 8.067us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 6.000s 176.726us 0 1 0.00
aes_control_fi 2.000s 127.605us 1 1 100.00
aes_cipher_fi 3.000s 130.533us 1 1 100.00
aes_ctr_fi 2.000s 84.324us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 6.000s 176.726us 0 1 0.00
aes_control_fi 2.000s 127.605us 1 1 100.00
aes_cipher_fi 3.000s 130.533us 1 1 100.00
aes_ctr_fi 2.000s 84.324us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 6.000s 176.726us 0 1 0.00
aes_control_fi 2.000s 127.605us 1 1 100.00
aes_ctr_fi 2.000s 84.324us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 6.000s 176.726us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 6.000s 176.726us 0 1 0.00
aes_control_fi 2.000s 127.605us 1 1 100.00
aes_cipher_fi 3.000s 130.533us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 10.603us 0 1 0.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1113): Assertion AesModeValid has failed 1 test run
aes_alert_reset 66526414378587971418959380644878971109290482478177233916150984269864119785139 275
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 8066502 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[2].gen_fsm_n.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 8066502 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[1].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 8066502 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[0].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
UVM_ERROR @ 8066502 ps: (aes_core.sv:1113) [ASSERT FAILED] AesModeValid
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 90711877111116909320758149027263689249080092803408407873798311560914115200629 18490
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 2572011596059303658272265319976787706024628622745674118529879049184979238502 170
UVM_INFO @ 10602588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---