Simulation Results: aes/unmasked

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.19 %
  • code
  • 90.54 %
  • assert
  • 97.73 %
  • func
  • 76.29 %
  • block
  • 90.41 %
  • line
  • 92.49 %
  • branch
  • 82.04 %
  • toggle
  • 97.99 %
  • FSM
  • 89.63 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 59.739us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 78.736us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 122.469us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 72.896us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 852.760us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 5.000s 2107.430us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 86.649us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 72.896us 1 1 100.00
aes_csr_aliasing 5.000s 2107.430us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 78.736us 1 1 100.00
aes_config_error 3.000s 162.093us 1 1 100.00
aes_stress 4.000s 411.007us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 78.736us 1 1 100.00
aes_config_error 3.000s 162.093us 1 1 100.00
aes_stress 4.000s 411.007us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 411.007us 1 1 100.00
aes_b2b 6.000s 318.676us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 411.007us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 78.736us 1 1 100.00
aes_config_error 3.000s 162.093us 1 1 100.00
aes_stress 4.000s 411.007us 1 1 100.00
aes_alert_reset 3.000s 256.724us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 60.747us 1 1 100.00
aes_config_error 3.000s 162.093us 1 1 100.00
aes_alert_reset 3.000s 256.724us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 324.723us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 260.860us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 256.724us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 411.007us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 411.007us 1 1 100.00
aes_sideload 3.000s 218.681us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 341.560us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10802.143s 0.000us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 186.942us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 103.957us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 103.957us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 122.469us 1 1 100.00
aes_csr_rw 2.000s 72.896us 1 1 100.00
aes_csr_aliasing 5.000s 2107.430us 1 1 100.00
aes_same_csr_outstanding 2.000s 143.671us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 122.469us 1 1 100.00
aes_csr_rw 2.000s 72.896us 1 1 100.00
aes_csr_aliasing 5.000s 2107.430us 1 1 100.00
aes_same_csr_outstanding 2.000s 143.671us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 65.679us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 2.000s 171.159us 0 1 0.00
aes_control_fi 2.000s 59.529us 1 1 100.00
aes_cipher_fi 1.000s 71.495us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 3.000s 96.490us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 3.000s 96.490us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 3.000s 96.490us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 3.000s 96.490us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 111.095us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 1064.493us 1 1 100.00
aes_tl_intg_err 2.000s 173.445us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 173.445us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 256.724us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 96.490us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 96.490us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 78.736us 1 1 100.00
aes_stress 4.000s 411.007us 1 1 100.00
aes_alert_reset 3.000s 256.724us 1 1 100.00
aes_core_fi 3.000s 131.659us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 162.093us 1 1 100.00
aes_stress 4.000s 411.007us 1 1 100.00
aes_core_fi 3.000s 131.659us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 96.490us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 55.346us 1 1 100.00
aes_stress 4.000s 411.007us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 411.007us 1 1 100.00
aes_sideload 3.000s 218.681us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 55.346us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 55.346us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 55.346us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 55.346us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 55.346us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 411.007us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 411.007us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 171.159us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 171.159us 0 1 0.00
aes_control_fi 2.000s 59.529us 1 1 100.00
aes_cipher_fi 1.000s 71.495us 1 1 100.00
aes_ctr_fi 2.000s 74.768us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 171.159us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 171.159us 0 1 0.00
aes_control_fi 2.000s 59.529us 1 1 100.00
aes_cipher_fi 1.000s 71.495us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 71.495us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 171.159us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 171.159us 0 1 0.00
aes_control_fi 2.000s 59.529us 1 1 100.00
aes_ctr_fi 2.000s 74.768us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 171.159us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 171.159us 0 1 0.00
aes_control_fi 2.000s 59.529us 1 1 100.00
aes_cipher_fi 1.000s 71.495us 1 1 100.00
aes_ctr_fi 2.000s 74.768us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 256.724us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 171.159us 0 1 0.00
aes_control_fi 2.000s 59.529us 1 1 100.00
aes_cipher_fi 1.000s 71.495us 1 1 100.00
aes_ctr_fi 2.000s 74.768us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 171.159us 0 1 0.00
aes_control_fi 2.000s 59.529us 1 1 100.00
aes_cipher_fi 1.000s 71.495us 1 1 100.00
aes_ctr_fi 2.000s 74.768us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 171.159us 0 1 0.00
aes_control_fi 2.000s 59.529us 1 1 100.00
aes_ctr_fi 2.000s 74.768us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 171.159us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 171.159us 0 1 0.00
aes_control_fi 2.000s 59.529us 1 1 100.00
aes_cipher_fi 1.000s 71.495us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 15.000s 619.959us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 91900307280427799121442636531696378344459683458060695124948121357361217000445 3896
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 1
----| Expected corrupted: 0
Job timed out after * minutes 1 test run
aes_stress_all 108627007063218493436882481931523219488655632446734489844189847983449889419925 None
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 107659956850044630793062453570639225280964247615401558824606871062477031972935 867
UVM_INFO @ 619959140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---