Simulation Results: chip

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 70.95 %
  • code
  • 80.80 %
  • assert
  • 97.48 %
  • func
  • 34.57 %
  • line
  • 93.67 %
  • branch
  • 93.40 %
  • cond
  • 88.01 %
  • toggle
  • 71.79 %
  • FSM
  • 57.14 %
Validation stages
V1
94.12%
V2
82.13%
V2S
100.00%
V3
58.33%
unmapped
12.50%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 3 3 100.00
chip_sw_example_rom 137.170s 3377.207us 1 1 100.00
chip_sw_example_manufacturer 204.740s 3372.693us 1 1 100.00
chip_sw_example_concurrency 221.680s 3285.731us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 274.190s 5774.487us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 676.950s 7570.653us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 2199.670s 25729.119us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 5825.760s 37422.904us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 80.930s 2574.316us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 5825.760s 37422.904us 1 1 100.00
chip_csr_rw 676.950s 7570.653us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 9.260s 190.610us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 461.030s 5494.833us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 461.030s 5494.833us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 461.030s 5494.833us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 449.130s 4883.735us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 449.130s 4883.735us 1 1 100.00
chip_sw_uart_tx_rx_idx1 424.790s 4527.881us 1 1 100.00
chip_sw_uart_tx_rx_idx2 421.110s 4982.856us 1 1 100.00
chip_sw_uart_tx_rx_idx3 470.160s 5033.619us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 368.140s 3787.633us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 467.050s 4031.918us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 864.320s 9661.712us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 342.180s 9038.175us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 342.180s 9038.175us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 284.080s 3260.543us 1 1 100.00
chip_sw_sleep_pin_wake 0 1 0.00
chip_sw_sleep_pin_wake 238.120s 3896.824us 0 1 0.00
chip_sw_sleep_pin_retention 0 1 0.00
chip_sw_sleep_pin_retention 250.160s 4314.916us 0 1 0.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 572.080s 8656.800us 1 1 100.00
chip_tap_straps_testunlock0 148.430s 3546.581us 1 1 100.00
chip_tap_straps_rma 199.180s 4388.038us 1 1 100.00
chip_tap_straps_prod 147.950s 3621.258us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 563.240s 6317.073us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 563.240s 6317.073us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 937.310s 10547.821us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1704.500s 14232.454us 0 1 0.00
chip_sw_ast_sys_clk_jitter 8 8 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4143.100s 19907.769us 1 1 100.00
chip_sw_aes_enc_jitter_en 231.070s 3709.450us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 761.220s 7704.984us 1 1 100.00
chip_sw_hmac_enc_jitter_en 213.890s 3548.963us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 1530.690s 11564.333us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 271.960s 3492.080us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 453.390s 5370.573us 1 1 100.00
chip_sw_clkmgr_jitter 218.330s 3142.250us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 241.820s 3988.890us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 1 2 50.00
chip_sw_sensor_ctrl_alert 480.880s 4741.755us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 199.780s 3328.798us 0 1 0.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 200.530s 2898.079us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 0 1 0.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 199.780s 3328.798us 0 1 0.00
chip_sw_smoketest 16 16 100.00
chip_sw_aes_smoketest 262.940s 3049.314us 1 1 100.00
chip_sw_aon_timer_smoketest 234.710s 3423.846us 1 1 100.00
chip_sw_clkmgr_smoketest 261.550s 3882.876us 1 1 100.00
chip_sw_csrng_smoketest 198.010s 3778.844us 1 1 100.00
chip_sw_entropy_src_smoketest 1000.800s 7279.083us 1 1 100.00
chip_sw_gpio_smoketest 327.080s 3959.763us 1 1 100.00
chip_sw_hmac_smoketest 296.190s 3446.881us 1 1 100.00
chip_sw_kmac_smoketest 265.280s 3988.320us 1 1 100.00
chip_sw_otbn_smoketest 755.590s 6293.966us 1 1 100.00
chip_sw_pwrmgr_smoketest 552.030s 8142.272us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 501.270s 8116.332us 1 1 100.00
chip_sw_rv_plic_smoketest 233.050s 4086.845us 1 1 100.00
chip_sw_rv_timer_smoketest 237.400s 4333.478us 1 1 100.00
chip_sw_rstmgr_smoketest 237.910s 2996.869us 1 1 100.00
chip_sw_sram_ctrl_smoketest 213.540s 3352.974us 1 1 100.00
chip_sw_uart_smoketest 199.500s 3743.993us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 235.730s 3794.637us 1 1 100.00
chip_sw_rom_functests 1 1 100.00
rom_keymgr_dpe_functest 442.480s 5984.531us 1 1 100.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 20315.910s 129018.642us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3381.650s 15462.840us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 540.850s 11733.419us 0 1 0.00
chip_sw_power_idle_load 1 1 100.00
chip_sw_power_idle_load 478.190s 5102.490us 1 1 100.00
chip_sw_power_sleep_load 1 1 100.00
chip_sw_power_sleep_load 473.420s 11309.600us 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 13200.146s 0.000us 0 1 0.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 94.360s 2248.959us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 94.360s 2248.959us 0 1 0.00
tl_d_outstanding_access 3 4 75.00
chip_csr_aliasing 5825.760s 37422.904us 1 1 100.00
chip_same_csr_outstanding 1898.270s 19557.216us 0 1 0.00
chip_csr_hw_reset 274.190s 5774.487us 1 1 100.00
chip_csr_rw 676.950s 7570.653us 1 1 100.00
tl_d_partial_access 3 4 75.00
chip_csr_aliasing 5825.760s 37422.904us 1 1 100.00
chip_same_csr_outstanding 1898.270s 19557.216us 0 1 0.00
chip_csr_hw_reset 274.190s 5774.487us 1 1 100.00
chip_csr_rw 676.950s 7570.653us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 33.590s 975.121us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 5.490s 40.934us 1 1 100.00
xbar_smoke_large_delays 49.410s 7869.017us 1 1 100.00
xbar_smoke_slow_rsp 31.340s 3190.358us 1 1 100.00
xbar_random_zero_delays 29.440s 462.977us 1 1 100.00
xbar_random_large_delays 153.070s 22825.479us 1 1 100.00
xbar_random_slow_rsp 148.410s 14148.099us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 19.020s 566.054us 1 1 100.00
xbar_error_and_unmapped_addr 12.350s 108.513us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 46.630s 2050.517us 1 1 100.00
xbar_error_and_unmapped_addr 12.350s 108.513us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 45.650s 631.907us 1 1 100.00
xbar_access_same_device_slow_rsp 33.700s 2840.652us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 16.300s 231.630us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 72.290s 1332.109us 1 1 100.00
xbar_stress_all_with_error 97.630s 2292.095us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 216.440s 5243.247us 1 1 100.00
xbar_stress_all_with_reset_error 149.080s 505.842us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3381.650s 15462.840us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2758.940s 32464.282us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 3296.490s 16226.846us 1 1 100.00
rom_e2e_boot_policy_valid 15 15 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2604.730s 11699.481us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 3823.630s 16613.203us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 3775.210s 16874.029us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 3724.090s 16650.091us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 3601.160s 17818.559us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 2737.760s 12218.378us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 3956.150s 20941.741us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 3713.710s 17225.486us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 3706.190s 18226.583us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 3580.330s 15450.049us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 4928.180s 18483.902us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 6604.990s 25648.493us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 6500.770s 25499.778us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 6508.690s 27293.080us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 6031.310s 24173.752us 1 1 100.00
rom_e2e_sigverify_always 15 15 100.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 5124.850s 24449.607us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 5912.810s 25757.237us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 6622.270s 33324.512us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 5945.110s 25157.461us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 5880.630s 25664.855us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 2884.570s 14470.454us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 3690.980s 24732.162us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 3346.480s 18142.932us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 3557.020s 17716.434us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 3584.210s 19685.939us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 2785.760s 13743.058us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 3309.880s 16408.486us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 3417.080s 15998.777us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 3254.900s 15005.426us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 3355.780s 17464.855us 1 1 100.00
rom_e2e_asm_init 4 5 80.00
rom_e2e_asm_init_test_unlocked0 2741.200s 11619.121us 1 1 100.00
rom_e2e_asm_init_dev 3762.300s 16236.498us 1 1 100.00
rom_e2e_asm_init_prod 732.600s 10010.240us 0 1 0.00
rom_e2e_asm_init_prod_end 3502.950s 15837.089us 1 1 100.00
rom_e2e_asm_init_rma 3362.680s 16300.573us 1 1 100.00
rom_e2e_keymgr_dpe_init 3 3 100.00
rom_e2e_keymgr_dpe_init_rom_ext_meas 7140.650s 30642.524us 1 1 100.00
rom_e2e_keymgr_dpe_init_rom_ext_no_meas 7112.710s 35626.557us 1 1 100.00
rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas 7349.970s 30256.385us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3981.630s 20811.319us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.185s 0.000us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.185s 0.000us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 318.820s 3848.534us 1 1 100.00
chip_sw_aes_enc_jitter_en 231.070s 3709.450us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 235.010s 2942.991us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 241.250s 3323.207us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_dpe_sideload_aes 1159.470s 8528.446us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 248.050s 3652.786us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 534.410s 6395.913us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 538.490s 6911.072us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 562.510s 5092.174us 1 1 100.00
chip_plic_all_irqs_10 387.500s 4419.080us 1 1 100.00
chip_plic_all_irqs_20 441.010s 4677.575us 1 1 100.00
chip_sw_alert_handler_entropy 0 1 0.00
chip_sw_alert_handler_entropy 253.820s 3280.510us 0 1 0.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1503.550s 14731.362us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 426.780s 6620.583us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 254.540s 3525.277us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 351.860s 3746.166us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 919.220s 7221.855us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1321.450s 8276.932us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 958.070s 8386.579us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 10801.660s 257803.996us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 378.090s 5519.263us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 552.030s 8142.272us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 378.090s 5519.263us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 671.960s 7659.355us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 671.960s 7659.355us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 471.350s 9200.795us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 517.700s 5428.404us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 755.060s 6888.566us 1 1 100.00
chip_sw_aes_idle 241.250s 3323.207us 1 1 100.00
chip_sw_hmac_enc_idle 238.400s 3313.139us 1 1 100.00
chip_sw_kmac_idle 258.520s 3861.988us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 346.740s 5537.170us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 406.930s 5662.596us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 396.470s 5700.775us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 443.810s 5322.890us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 1006.850s 16283.614us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 551.720s 4837.452us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 524.110s 5785.803us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 531.190s 4567.405us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 518.680s 5480.593us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 499.430s 4368.723us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 482.250s 4490.174us 1 1 100.00
chip_sw_ast_clk_outputs 937.310s 10547.821us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1575.440s 21767.828us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 531.190s 4567.405us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 518.680s 5480.593us 1 1 100.00
chip_sw_clkmgr_jitter 8 8 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4143.100s 19907.769us 1 1 100.00
chip_sw_aes_enc_jitter_en 231.070s 3709.450us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 761.220s 7704.984us 1 1 100.00
chip_sw_hmac_enc_jitter_en 213.890s 3548.963us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 1530.690s 11564.333us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 271.960s 3492.080us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 453.390s 5370.573us 1 1 100.00
chip_sw_clkmgr_jitter 218.330s 3142.250us 1 1 100.00
chip_sw_clkmgr_extended_range 8 8 100.00
chip_sw_clkmgr_jitter_reduced_freq 235.420s 3156.888us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4237.030s 25926.096us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 254.070s 4092.578us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 276.400s 4014.523us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq 1571.050s 13633.665us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 239.460s 4145.584us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 542.000s 6215.890us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 2802.860s 19617.521us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 937.310s 10547.821us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 0 1 0.00
chip_sw_clkmgr_sleep_frequency 466.250s 5645.871us 0 1 0.00
chip_sw_clkmgr_reset_frequency 0 1 0.00
chip_sw_clkmgr_reset_frequency 447.890s 4414.896us 0 1 0.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 538.490s 6911.072us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 919.220s 7221.855us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 1212.750s 7222.873us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 475.360s 6288.339us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 825.600s 13103.321us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 227.140s 3860.591us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 3812.250s 19900.618us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 207.600s 2919.957us 1 1 100.00
chip_sw_edn_entropy_reqs 942.680s 8673.541us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 207.600s 2919.957us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 1212.750s 7222.873us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 259.080s 3545.354us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 207.930s 3773.139us 1 1 100.00
chip_sw_hmac_enc_jitter_en 213.890s 3548.963us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 238.400s 3313.139us 1 1 100.00
chip_sw_hmac_all_configurations 0 1 0.00
chip_sw_hmac_oneshot 1520.090s 12027.022us 0 1 0.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 2164.770s 12018.542us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 617.670s 6200.255us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 507.700s 4604.204us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 499.210s 5594.682us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 321.720s 4315.275us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 2 2 100.00
chip_sw_keymgr_dpe_key_derivation 947.600s 8164.197us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 1530.690s 11564.333us 1 1 100.00
chip_sw_keymgr_dpe_sideload_kmac 1 1 100.00
chip_sw_keymgr_dpe_sideload_kmac 2200.230s 14267.230us 1 1 100.00
chip_sw_keymgr_dpe_sideload_aes 1 1 100.00
chip_sw_keymgr_dpe_sideload_aes 1159.470s 8528.446us 1 1 100.00
chip_sw_keymgr_dpe_sideload_otbn 0 1 0.00
chip_sw_keymgr_dpe_sideload_otbn 3600.142s 0.000us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 283.420s 3922.325us 1 1 100.00
chip_sw_kmac_mode_kmac 234.360s 3335.954us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 271.960s 3492.080us 1 1 100.00
chip_sw_kmac_app_keymgr_dpe 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 947.600s 8164.197us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 1678.540s 29835.196us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 263.280s 3755.373us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 628.190s 5816.924us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 258.520s 3861.988us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 534.410s 6395.913us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 572.080s 8656.800us 1 1 100.00
chip_tap_straps_rma 199.180s 4388.038us 1 1 100.00
chip_tap_straps_prod 147.950s 3621.258us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 292.050s 4025.131us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 1678.540s 29835.196us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 1678.540s 29835.196us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 1678.540s 29835.196us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_dpe_key_derivation_prod 1765.130s 12390.400us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 21 90.48
chip_sw_rram_rma_unlocked 8119.110s 96653.095us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 274.000s 3209.987us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 849.880s 8215.285us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 816.960s 8972.166us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 666.690s 6644.960us 0 1 0.00
chip_sw_lc_ctrl_transition 1678.540s 29835.196us 1 1 100.00
chip_sw_rram_ctrl_lc_rw_en 569.990s 6159.248us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 947.600s 8164.197us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 585.900s 10390.064us 1 1 100.00
chip_sw_sram_ctrl_execution_main 810.790s 11338.445us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1575.440s 21767.828us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 551.720s 4837.452us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 524.110s 5785.803us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 531.190s 4567.405us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 518.680s 5480.593us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 499.430s 4368.723us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 482.250s 4490.174us 1 1 100.00
chip_tap_straps_dev 572.080s 8656.800us 1 1 100.00
chip_tap_straps_rma 199.180s 4388.038us 1 1 100.00
chip_tap_straps_prod 147.950s 3621.258us 1 1 100.00
chip_rv_dm_lc_disabled 78.320s 2940.274us 0 1 0.00
chip_lc_scrap 0 4 0.00
chip_sw_lc_ctrl_rma_to_scrap 495.670s 7211.840us 0 1 0.00
chip_sw_lc_ctrl_raw_to_scrap 2495.740s 60000.000us 0 1 0.00
chip_sw_lc_ctrl_test_locked0_to_scrap 2758.380s 60000.000us 0 1 0.00
chip_sw_lc_ctrl_rand_to_scrap 1888.430s 60000.000us 0 1 0.00
chip_lc_test_locked 0 2 0.00
chip_sw_lc_walkthrough_testunlocks 3312.640s 60000.000us 0 1 0.00
chip_rv_dm_lc_disabled 78.320s 2940.274us 0 1 0.00
chip_sw_lc_walkthrough 1 5 20.00
chip_sw_lc_walkthrough_dev 1795.530s 21947.273us 0 1 0.00
chip_sw_lc_walkthrough_prod 1569.290s 20500.555us 0 1 0.00
chip_sw_lc_walkthrough_prodend 1778.250s 27013.732us 1 1 100.00
chip_sw_lc_walkthrough_rma 1079.400s 14216.142us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 3312.640s 60000.000us 0 1 0.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 285.950s 7053.736us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 243.860s 5390.318us 1 1 100.00
rom_volatile_raw_unlock 283.570s 6017.192us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3968.330s 18686.942us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4143.100s 19907.769us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 755.060s 6888.566us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 755.060s 6888.566us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 755.060s 6888.566us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 365.160s 4345.337us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 1678.540s 29835.196us 1 1 100.00
chip_sw_otp_ctrl_keys 4 4 100.00
chip_sw_otbn_mem_scramble 365.160s 4345.337us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 947.600s 8164.197us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 558.170s 5961.685us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 218.160s 3175.145us 1 1 100.00
chip_sw_otp_ctrl_entropy 4 4 100.00
chip_sw_otbn_mem_scramble 365.160s 4345.337us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 947.600s 8164.197us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 558.170s 5961.685us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 218.160s 3175.145us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 1678.540s 29835.196us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 504.840s 6072.384us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 292.050s 4025.131us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 4 5 80.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 274.000s 3209.987us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 849.880s 8215.285us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 816.960s 8972.166us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 666.690s 6644.960us 0 1 0.00
chip_sw_lc_ctrl_transition 1678.540s 29835.196us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1031.950s 8741.092us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 279.380s 6586.607us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 212.990s 3845.197us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 223.430s 4382.815us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 461.540s 9319.595us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 403.370s 7353.511us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1085.980s 23532.984us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 572.770s 11260.195us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 671.960s 7659.355us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 274.660s 3203.022us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 617.590s 6891.939us 1 1 100.00
chip_sw_pwrmgr_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 279.380s 6586.607us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 424.040s 5816.527us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 294.420s 4123.330us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 345.010s 6922.220us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 219.530s 3254.069us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 285.250s 6510.315us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 866.960s 10063.108us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1071.070s 12130.990us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2281.480s 33913.548us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 225.000s 3130.103us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 538.490s 6911.072us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 585.900s 10390.064us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 585.900s 10390.064us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1071.070s 12130.990us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 285.250s 6510.315us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 617.590s 6891.939us 1 1 100.00
chip_sw_pwrmgr_smoketest 552.030s 8142.272us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 367.890s 5308.170us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 720.900s 8903.158us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 382.490s 4496.434us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1503.550s 14731.362us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 287.160s 3850.901us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 538.490s 6911.072us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1321.450s 8276.932us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 545.930s 6038.154us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 689.350s 6275.222us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 202.920s 2981.287us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 218.160s 3175.145us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 720.900s 8903.158us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 720.900s 8903.158us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 249.110s 3170.365us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1511.520s 18449.413us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 1372.990s 17255.332us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 367.890s 5308.170us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 278.590s 3522.419us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 249.090s 3434.761us 0 1 0.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 199.180s 4388.038us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 78.320s 2940.274us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 562.510s 5092.174us 1 1 100.00
chip_plic_all_irqs_10 387.500s 4419.080us 1 1 100.00
chip_plic_all_irqs_20 441.010s 4677.575us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 258.040s 4100.579us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 243.230s 3777.211us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3381.650s 15462.840us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 326.150s 4072.725us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 289.620s 3238.555us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 281.930s 3266.325us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 232.040s 4155.498us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 558.170s 5961.685us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 453.390s 5370.573us 1 1 100.00
chip_sw_sleep_sram_ret_contents 0 2 0.00
chip_sw_sleep_sram_ret_contents_no_scramble 267.350s 3940.769us 0 1 0.00
chip_sw_sleep_sram_ret_contents_scramble 200.250s 3305.091us 0 1 0.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 810.790s 11338.445us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 538.490s 6911.072us 1 1 100.00
chip_sw_data_integrity_escalation 563.240s 6317.073us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1 2 50.00
chip_sw_pwrmgr_sysrst_ctrl_reset 866.960s 10063.108us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1245.720s 24450.980us 0 1 0.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 223.200s 3056.875us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 338.480s 4520.155us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 423.510s 5054.526us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 0 1 0.00
chip_sw_sysrst_ctrl_reset 1245.720s 24450.980us 0 1 0.00
chip_sw_sysrst_ctrl_sleep_reset 0 1 0.00
chip_sw_sysrst_ctrl_reset 1245.720s 24450.980us 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 293.160s 5010.320us 0 1 0.00
chip_sw_sysrst_ctrl_flash_wp_l 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 293.160s 5010.320us 0 1 0.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 520.860s 9060.221us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.185s 0.000us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 238.420s 4190.283us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 271.920s 4383.608us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 338.070s 4386.521us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 409.010s 4681.117us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1122.190s 8767.377us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5919.680s 32246.208us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 2086.230s 12644.207us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 239.180s 4381.983us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 292.320s 3725.153us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 146.470s 2218.963us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 12409.330s 72768.141us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1363.670s 7144.719us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 252.200s 4175.580us 0 1 0.00
rom_e2e_jtag_debug_dev 319.660s 5400.780us 0 1 0.00
rom_e2e_jtag_debug_rma 239.430s 3950.933us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 178.200s 3430.004us 0 1 0.00
rom_e2e_jtag_inject_dev 105.980s 2680.109us 0 1 0.00
rom_e2e_jtag_inject_rma 146.080s 2958.526us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 38.951s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 309.170s 4429.112us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 380.370s 3681.332us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 1218.720s 7108.158us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1492.480s 9785.660us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 325.420s 3577.170us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 365.990s 4451.320us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 418.000s 7928.978us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 410.110s 4921.906us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1071.070s 12130.990us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 252.200s 4175.580us 0 1 0.00
rom_e2e_jtag_debug_dev 319.660s 5400.780us 0 1 0.00
rom_e2e_jtag_debug_rma 239.430s 3950.933us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 436.190s 5641.949us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 538.490s 6911.072us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 6298.630s 38463.879us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 6298.630s 38463.879us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 0 1 0.00
chip_sw_spi_device_pinmux_sleep_retention 216.650s 2989.752us 0 1 0.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 449.130s 4883.735us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3529.200s 19010.188us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 8 12.50
chip_sw_rstmgr_rst_cnsty_escalation 40.200s 10.300us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 134.500s 3414.515us 0 1 0.00
chip_sw_otp_ctrl_descrambling 313.850s 4208.397us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 261.010s 4022.577us 0 1 0.00
chip_sw_pwrmgr_sleep_wake_5_bug 12.318s 0.000us 0 1 0.00
ate_bootstrap_flash_erase 752.600s 10010.400us 0 1 0.00
ate_bootstrap_one_frame 10800.159s 0.000us 0 1 0.00
ate_bootstrap_disjoint 10800.145s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:254) scoreboard [scoreboard] alert fatal has unexpected signal int error 14 test runs
chip_sw_sleep_pin_wake 113610692036744863283084178008014508294055588122301268906359083689858122833359 380
UVM_INFO @ 3896.824472 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_retention 22099080484219176546317995733403905857728265433073285704515374155764098948694 377
UVM_INFO @ 4314.915872 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pinmux_sleep_retention 69586803032952556384962865384758815814836687696777925157010299263801295144025 372
UVM_INFO @ 2989.751812 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 69294778616609187115359133844232582373314761040853125717748673929442268582794 375
UVM_INFO @ 3203.022066 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_por_reset 24016588745528776669204949392380329638584218269500742512379383526943673662987 386
UVM_INFO @ 7353.510930 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 75281376712365189262817020999276716814413485910594374202864444862410930839986 377
UVM_INFO @ 4123.329746 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_no_scramble 12646353593297725686249761490548843315532712762488456347950654318640435817442 375
UVM_INFO @ 3940.768632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_scramble 108234648781656869526621996815639034079735016384506744225126129210308653066823 379
UVM_INFO @ 3305.090928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 60998960090721867424318420256186211666559147469137751585462147226764837042684 370
UVM_INFO @ 3328.798220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_sleep_frequency 1444206088996209168458676549346036037562000974285824883149915318260145589384 405
UVM_INFO @ 5645.871336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_wake_ups 6164302640552297748748242994782623128195132351149839116689969568477222565645 372
UVM_INFO @ 4382.814888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_lowpower_cancel 101061003879381577621398152802917099022776329435021092390335393120640747280371 370
UVM_INFO @ 4022.577192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_wake_ups 5780208151806028886009231348669789860224426852038893203364170537802996707415 371
UVM_INFO @ 3845.196684 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_dm_access_after_wakeup 98949954382360290577055919484376552019904935959552342167792531415503929193840 382
UVM_INFO @ 3434.760810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access 8 test runs
chip_sw_otp_ctrl_rot_auth_config 75776905243932838029422500720198472620101642222700056710676669314857021147182 373
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 8480857077446573021361841483425262832687849273341351671918647820742642926289 395
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 35525625907486388575676793524074229463763597588671617468121181279342346887399 387
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 8133268646530118745123769254219631941257209000750908269272398244516684296238 387
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 68033217057004898678738639310514093336741883979699767718516796002012819087921 387
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 71666037210848710411517661428208870661045490779213898051136875010816237424636 371
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 32587876890977585407578075270919639509778505277768388736668626809583597156141 373
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 46377437910614931180647730798260039184406828734268972438071870219779021776843 371
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
Job timed out after * minutes 5 test runs
chip_sw_exit_test_unlocked_bootstrap 19296660244371889615712444814021816135608177082053920048408893931330683139099 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 93291974705042042079609374038233847434481466654098149345401269860259346821147 None
chip_sw_keymgr_dpe_sideload_otbn 102376760926298216023030396750980118977405313205933886389113474684358753308171 None
ate_bootstrap_one_frame 16061710981944622410409241570015730863026405893544455213681680161463961643815 None
ate_bootstrap_disjoint 41408456638883684751534269385602943270839488124978147135281021304005350576028 None
Offending '(rstreqs[*] && (reset_cause == HwReq))' 5 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 68054039441204641092673932866468029253395652944149117125943314785089271738474 377
UVM_ERROR @ 6510.315000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6510.315000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 66266480780243190797267271188981008577710364641521616641352035140045705517262 389
UVM_ERROR @ 11260.195000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 11260.195000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 25033952181989800971513770235543763606406685507617036236735799395852809817060 387
UVM_ERROR @ 9319.595500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9319.595500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sysrst_ctrl_reset 53532240450680877284379398430916856054749759204054754638868294800217666334156 396
UVM_ERROR @ 24450.980000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 24450.980000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 111405538564812735295884340865973975276686785207367868998171418952335638591775 381
UVM_ERROR @ 7659.355000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7659.355000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue 4 test runs
chip_sw_lc_ctrl_raw_to_scrap 82771360293268857241893405498490138959224079605626527939559905442819189421728 375
UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_ctrl_test_locked0_to_scrap 99396505020137931346611615205785293395883614347553778158022796903987600144595 375
UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_ctrl_rand_to_scrap 34943031390671660025329823433714875633180934474305540424838035003881345067788 375
UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_testunlocks 97985942459370171250150854329897312089720474345500323798154369898803366978274 511
UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 16306450849131382192392138971303492857644133434292719408018164229611756684469 431
UVM_INFO @ 21947.273352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 24092480684103809635622721935543442236790730360984961947239432421325896969070 431
UVM_INFO @ 20500.555030 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 114825957606541294739425749540440444890915591729336120745139783015609542775808 403
UVM_INFO @ 14216.141788 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error 2 test runs
chip_sw_alert_handler_lpg_sleep_mode_pings 99521007848591330598551008704767467559573756083692474177853765024683544709949 371
UVM_INFO @ 3746.165688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_entropy 371374331537746051806541693612770018072728720955761590204362832610105223867 449
UVM_INFO @ 3280.509636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:335) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 2 test runs
chip_sw_hmac_oneshot 8859857570502803406442161651201123476917218728205809103081001481549962853303 372
UVM_INFO @ 12027.022301 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_multistream 50015829639617654825076722192175460842362938536963548993760281883315672127469 441
UVM_INFO @ 12018.542415 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:689) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 99617362080892505819866984029029724628012360328289557696788293423805088360043 280
TL item was: req: (cip_tl_seq_item@81362) { a_addr: 'h10770 a_data: 'h3b0002d5 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h4 a_user: 'h18d28 d_param: 'h0 d_source: 'h29 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2248.959458 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 18812437513543898649396293413014111328178748137962362202181824599380887852824 284
TL item was: req: (cip_tl_seq_item@80696) { a_addr: 'h105a0 a_data: 'hf0725e2b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h4 a_user: 'h1ba97 d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2574.315720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 2 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 58824959549315171673693728853226658948241048937193636723781709663102474965030 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 14284472240973831652528730520910464552166770652902647516272579803748786487194 None
Another command (pid=459137) is running. Waiting for it to complete on the server (server_pid=208358)...
Another command (pid=459758) is running. Waiting for it to complete on the server (server_pid=208358)...
Another command (pid=472008) is running. Waiting for it to complete on the server (server_pid=208358)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_ERROR @ * us: (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal triggered unexpectedly 1 test run
chip_same_csr_outstanding 62993646187004922551233536693656448482928124365499424737244854852825549478328 281
UVM_INFO @ 19557.216072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 50269771290480896741717800584700832112908936603935222032912303543200916434870 363
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 97593624334295761920969072229945618239152738418290269801162672106995298188888 389
UVM_INFO @ 3238.555380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 106478163559663397378371772318452286117448014661135142987039186985762094300296 402
UVM_INFO @ 6644.959760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:715)] CHECK-fail: Alert handler NMI state not expected: 1 test run
chip_sw_otp_ctrl_escalation 2377662127155845505243860166694901593647214228058796395187260839835101857353 377
alert_enable:1
alert_raised:0
UVM_INFO @ 4451.319509 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:882) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl 1 test run
chip_sw_lc_ctrl_rma_to_scrap 35253844283638668174479147278012328566164911003306388943245537411046517923876 375
UVM_INFO @ 7211.840213 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 13281856996206788911779613031435471751421584145551827580472353043535722380257 388
UVM_ERROR @ 6586.607050 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 6586.607050 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 1 test run
chip_sw_pwrmgr_sleep_power_glitch_reset 1143605566072314158083191352852013798115708697754562081041212225207239316358 375
UVM_ERROR @ 3254.069370 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3254.069370 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_sysrst_ctrl_ec_rst_l_vseq.sv:138) [chip_sw_sysrst_ctrl_ec_rst_l_vseq] Timed out waiting for ec_rst to go high. 1 test run
chip_sw_sysrst_ctrl_ec_rst_l 61099727916828966914367257041596082154661760830010335984951699758772526545020 373
UVM_INFO @ 5010.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:301)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 69400709517859128186467671343473532747341624910762114770790569274348654865623 369
UVM_INFO @ 3652.786032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 25657940321919640946208189575829114792288137506112368350062337745708436474912 371
UVM_INFO @ 3525.277048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state. 1 test run
chip_sw_clkmgr_reset_frequency 57627454734840479794024895546833939022248497274833427368873242505844687520645 398
UVM_INFO @ 4414.896176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 97127309760980016382197022048544917970317843192866919635371141818354753636010 405
UVM_INFO @ 4429.111855 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 23189965353082571964797497935984450701179969287615448944868597067547118154894 284
UVM_INFO @ 2940.274008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 66756753223495085725983471487597162104758140097466621774409532774117821739132 389
UVM_INFO @ 14232.453552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 61916394279017966390746541208154854023723892098605852711523995246693094350258 337
UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rom_e2e_asm_init_vseq.sv:44) [chip_sw_rom_e2e_asm_init_vseq] wait timeout occurred! 1 test run
rom_e2e_asm_init_prod 57752512054697884656428741871408713532822296694478348917611253380560597580679 367
UVM_INFO @ 10010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:882) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl 1 test run
rom_raw_unlock 40228592296835138118577653412074564875359342351668422323355832937727567273505 376
UVM_INFO @ 11733.419146 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---