Simulation Results: csrng

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 82.96 %
  • code
  • 92.13 %
  • assert
  • 93.45 %
  • func
  • 63.31 %
  • block
  • 96.75 %
  • line
  • 97.55 %
  • branch
  • 92.01 %
  • toggle
  • 93.24 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 116.607us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 37.606us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 1.000s 12.345us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 13.000s 341.260us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 7.000s 347.014us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 4.000s 170.216us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 1.000s 12.345us 1 1 100.00
csrng_csr_aliasing 7.000s 347.014us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 133.457us 1 1 100.00
alerts 1 1 100.00
csrng_alert 11.000s 421.349us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 27.762us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 5.000s 108.110us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 5.000s 108.110us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 11.000s 177.742us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 20.621us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 49.863us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 77.427us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 77.427us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 37.606us 1 1 100.00
csrng_csr_rw 1.000s 12.345us 1 1 100.00
csrng_csr_aliasing 7.000s 347.014us 1 1 100.00
csrng_same_csr_outstanding 3.000s 58.049us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 37.606us 1 1 100.00
csrng_csr_rw 1.000s 12.345us 1 1 100.00
csrng_csr_aliasing 7.000s 347.014us 1 1 100.00
csrng_same_csr_outstanding 3.000s 58.049us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 4.000s 288.006us 1 1 100.00
csrng_tl_intg_err 4.000s 94.960us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 1.000s 1.579us 0 1 0.00
csrng_csr_rw 1.000s 12.345us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 11.000s 421.349us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 11.000s 177.742us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 133.457us 1 1 100.00
csrng_err 2.000s 27.762us 1 1 100.00
csrng_sec_cm 4.000s 288.006us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 133.457us 1 1 100.00
csrng_err 2.000s 27.762us 1 1 100.00
csrng_sec_cm 4.000s 288.006us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 133.457us 1 1 100.00
csrng_err 2.000s 27.762us 1 1 100.00
csrng_sec_cm 4.000s 288.006us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 133.457us 1 1 100.00
csrng_err 2.000s 27.762us 1 1 100.00
csrng_sec_cm 4.000s 288.006us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 133.457us 1 1 100.00
csrng_err 2.000s 27.762us 1 1 100.00
csrng_sec_cm 4.000s 288.006us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 11.000s 421.349us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 133.457us 1 1 100.00
csrng_err 2.000s 27.762us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 11.000s 177.742us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 11.000s 421.349us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 94.960us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 133.457us 1 1 100.00
csrng_err 2.000s 27.762us 1 1 100.00
csrng_sec_cm 4.000s 288.006us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 133.457us 1 1 100.00
csrng_err 2.000s 27.762us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 133.457us 1 1 100.00
csrng_err 2.000s 27.762us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 133.457us 1 1 100.00
csrng_err 2.000s 27.762us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 133.457us 1 1 100.00
csrng_err 2.000s 27.762us 1 1 100.00
csrng_sec_cm 4.000s 288.006us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 133.457us 1 1 100.00
csrng_err 2.000s 27.762us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 102.000s 2252.134us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:667) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 13395865189196553294663582575760909663428403041927613356404347277158377302010 100
UVM_INFO @ 108109640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 1 test run
csrng_regwen 3395290743313917113166411875812993056264597718131901127033514644562341549881 99
UVM_INFO @ 1578694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started 1 test run
csrng_stress_all_with_rand_reset 65938159519617362137393287160559145400772847278908009135410220557926365162411 155
UVM_INFO @ 2252133914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---