Simulation Results: edn/edn0

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 88.37 %
  • code
  • 86.76 %
  • assert
  • 97.61 %
  • func
  • 80.75 %
  • line
  • 98.70 %
  • branch
  • 95.82 %
  • cond
  • 89.55 %
  • toggle
  • 94.34 %
  • FSM
  • 55.38 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.300s 27.404us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.280s 16.938us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.290s 17.358us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.310s 119.240us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.660s 82.094us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.740s 41.769us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.290s 17.358us 1 1 100.00
edn_csr_aliasing 1.660s 82.094us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.460s 59.929us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.460s 59.929us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.460s 59.929us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.350s 28.461us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.630s 157.682us 1 1 100.00
errs 1 1 100.00
edn_err 1.450s 18.192us 1 1 100.00
disable 2 2 100.00
edn_disable 1.270s 21.557us 1 1 100.00
edn_disable_auto_req_mode 1.500s 99.104us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.920s 431.140us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.250s 51.362us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.310s 97.969us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.190s 198.688us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.190s 198.688us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.280s 16.938us 1 1 100.00
edn_csr_rw 1.290s 17.358us 1 1 100.00
edn_csr_aliasing 1.660s 82.094us 1 1 100.00
edn_same_csr_outstanding 1.310s 15.079us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.280s 16.938us 1 1 100.00
edn_csr_rw 1.290s 17.358us 1 1 100.00
edn_csr_aliasing 1.660s 82.094us 1 1 100.00
edn_same_csr_outstanding 1.310s 15.079us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.070s 4172.490us 1 1 100.00
edn_tl_intg_err 2.170s 238.202us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.180s 98.194us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.630s 157.682us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.070s 4172.490us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.070s 4172.490us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.070s 4172.490us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.070s 4172.490us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.630s 157.682us 1 1 100.00
edn_sec_cm 6.070s 4172.490us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.630s 157.682us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.170s 238.202us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 55.290s 8383.388us 1 1 100.00