Simulation Results: edn/edn1

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 87.36 %
  • code
  • 83.14 %
  • assert
  • 98.70 %
  • func
  • 80.25 %
  • line
  • 97.88 %
  • branch
  • 92.42 %
  • cond
  • 88.15 %
  • toggle
  • 95.19 %
  • FSM
  • 42.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.110s 143.964us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.160s 45.329us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.960s 14.455us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.020s 321.990us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.490s 64.844us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.300s 22.734us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.960s 14.455us 1 1 100.00
edn_csr_aliasing 1.490s 64.844us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.900s 71.514us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.900s 71.514us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.900s 71.514us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.160s 29.292us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.530s 79.627us 1 1 100.00
errs 1 1 100.00
edn_err 1.420s 36.502us 1 1 100.00
disable 2 2 100.00
edn_disable 1.060s 17.903us 1 1 100.00
edn_disable_auto_req_mode 1.660s 41.288us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.540s 89.952us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.010s 15.781us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.280s 46.673us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.930s 57.086us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.930s 57.086us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.160s 45.329us 1 1 100.00
edn_csr_rw 0.960s 14.455us 1 1 100.00
edn_csr_aliasing 1.490s 64.844us 1 1 100.00
edn_same_csr_outstanding 1.530s 47.753us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.160s 45.329us 1 1 100.00
edn_csr_rw 0.960s 14.455us 1 1 100.00
edn_csr_aliasing 1.490s 64.844us 1 1 100.00
edn_same_csr_outstanding 1.530s 47.753us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.510s 688.174us 1 1 100.00
edn_tl_intg_err 1.990s 174.542us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.320s 17.430us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.530s 79.627us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.510s 688.174us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.510s 688.174us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.510s 688.174us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.510s 688.174us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.530s 79.627us 1 1 100.00
edn_sec_cm 6.510s 688.174us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.530s 79.627us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.990s 174.542us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 40.420s 4082.896us 1 1 100.00