Simulation Results: entropy_src/rng_4bits

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 76.53 %
  • code
  • 88.46 %
  • assert
  • 83.74 %
  • func
  • 57.40 %
  • block
  • 94.41 %
  • line
  • 97.04 %
  • branch
  • 86.75 %
  • toggle
  • 76.31 %
  • FSM
  • 93.75 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 3.000s 53.620us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 48.014us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 22.822us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 10.000s 226.887us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 6.000s 222.815us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 34.591us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 22.822us 1 1 100.00
entropy_src_csr_aliasing 6.000s 222.815us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 3.000s 53.620us 1 1 100.00
entropy_src_rng 263.000s 14020.113us 1 1 100.00
entropy_src_fw_ov 199.000s 14113.992us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 199.000s 14113.992us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 263.000s 14020.113us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 260.000s 14056.653us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 263.000s 14020.113us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 263.000s 14020.113us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 263.000s 14020.113us 1 1 100.00
entropy_src_intr 23.000s 2874.820us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 263.000s 14020.113us 1 1 100.00
entropy_src_functional_alerts 6.000s 330.070us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 286.000s 13129.274us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 125.740us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 3.000s 33.149us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 23.052us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 18.668us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 6.000s 146.915us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 6.000s 146.915us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 48.014us 1 1 100.00
entropy_src_csr_rw 2.000s 22.822us 1 1 100.00
entropy_src_csr_aliasing 6.000s 222.815us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 142.545us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 48.014us 1 1 100.00
entropy_src_csr_rw 2.000s 22.822us 1 1 100.00
entropy_src_csr_aliasing 6.000s 222.815us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 142.545us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 160.181us 1 1 100.00
entropy_src_tl_intg_err 4.000s 172.975us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 263.000s 14020.113us 1 1 100.00
entropy_src_cfg_regwen 2.000s 21.142us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 263.000s 14020.113us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 263.000s 14020.113us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 263.000s 14020.113us 1 1 100.00
entropy_src_fw_ov 199.000s 14113.992us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 125.740us 1 1 100.00
entropy_src_sec_cm 3.000s 160.181us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 125.740us 1 1 100.00
entropy_src_sec_cm 3.000s 160.181us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 263.000s 14020.113us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 125.740us 1 1 100.00
entropy_src_sec_cm 3.000s 160.181us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 125.740us 1 1 100.00
entropy_src_sec_cm 3.000s 160.181us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 125.740us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 6.000s 330.070us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 4.000s 172.975us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 245.000s 13047.206us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 4.000s 64.298us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 43612865350514387804459216265113487832332541012017908503185058607964274069757 165
UVM_INFO @ 64298401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_lo_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 113479649613152723084388196175662567373571767889645386157861231346863067188507 113
UVM_INFO @ 34590554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---