Simulation Results: flash_ctrl

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 94.32 %
  • code
  • 92.83 %
  • assert
  • 94.55 %
  • func
  • 95.57 %
  • line
  • 95.91 %
  • branch
  • 96.67 %
  • cond
  • 93.51 %
  • toggle
  • 92.35 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
86.21%
V2S
83.33%
V3
100.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 257.000s 104.574us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 117.790s 32.024us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 249.450s 182.551us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 103.900s 42.048us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 149.700s 16282.058us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 110.010s 447.536us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 100.890s 191.033us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 103.900s 42.048us 1 1 100.00
flash_ctrl_csr_aliasing 110.010s 447.536us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 73.480s 30.082us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 60.730s 83.834us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 122.230s 105.878us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 154.250s 137.053us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1669.490s 85808.897us 1 1 100.00
flash_ctrl_hw_rma_reset 856.920s 80157.572us 1 1 100.00
flash_ctrl_lcmgr_intg 79.830s 23.919us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 2785.210s 274806.010us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 1341.280s 4826.725us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 71.950s 38.599us 1 1 100.00
full_memory_access 0 1 0.00
flash_ctrl_full_mem_access 2325.180s 359049.473us 0 1 0.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 522.250s 219.268us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 123.570s 34.696us 1 1 100.00
flash_ctrl_rw_evict_all_en 119.700s 30.956us 1 1 100.00
flash_ctrl_re_evict 137.790s 556.515us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 909.560s 225.178us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 909.560s 225.178us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 489.470s 33131.191us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 110.870s 1091.072us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 2964.360s 653.677us 1 1 100.00
error_mp 0 1 0.00
flash_ctrl_error_mp 3600.134s 0.000us 0 1 0.00
error_prog_win 0 1 0.00
flash_ctrl_error_prog_win 3600.205s 0.000us 0 1 0.00
error_prog_type 0 1 0.00
flash_ctrl_error_prog_type 3600.132s 0.000us 0 1 0.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 84.040s 38.935us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 222.000s 2501.580us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 133.280s 23.942us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 83.100s 50.022us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 5789.680s 978.104us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 162.550s 7397.439us 1 1 100.00
flash_ctrl_otp_reset 553.160s 86.579us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1669.490s 85808.897us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 330.760s 5075.264us 1 1 100.00
flash_ctrl_intr_wr 151.500s 21873.202us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 357.590s 12050.071us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 208.150s 28461.263us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 106.660s 2374.665us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 156.600s 2830.993us 1 1 100.00
double_bit_err 3 5 60.00
flash_ctrl_read_word_sweep_derr 98.540s 109.438us 1 1 100.00
flash_ctrl_ro_derr 197.220s 3496.726us 1 1 100.00
flash_ctrl_rw_derr 2781.780s 200000.000us 0 1 0.00
flash_ctrl_derr_detect 610.140s 847.946us 1 1 100.00
flash_ctrl_integrity 232.000s 1487.690us 0 1 0.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 94.250s 31.270us 1 1 100.00
flash_ctrl_ro_serr 197.820s 6305.721us 1 1 100.00
flash_ctrl_rw_serr 207.350s 3735.062us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 122.820s 904.819us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 125.230s 3206.540us 1 1 100.00
scramble 3 5 60.00
flash_ctrl_wo 130.090s 2109.497us 1 1 100.00
flash_ctrl_write_word_sweep 60.680s 50.014us 1 1 100.00
flash_ctrl_read_word_sweep 66.540s 174.151us 1 1 100.00
flash_ctrl_ro 133.380s 712.169us 0 1 0.00
flash_ctrl_rw 406.450s 7227.402us 0 1 0.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 101.490s 793.065us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 772.240s 118780.594us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 259.820s 10034.254us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 103.970s 701.469us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 76.860s 124.049us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 64.870s 386.020us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 64.870s 386.020us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 249.450s 182.551us 1 1 100.00
flash_ctrl_csr_rw 103.900s 42.048us 1 1 100.00
flash_ctrl_csr_aliasing 110.010s 447.536us 1 1 100.00
flash_ctrl_same_csr_outstanding 129.710s 898.693us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 249.450s 182.551us 1 1 100.00
flash_ctrl_csr_rw 103.900s 42.048us 1 1 100.00
flash_ctrl_csr_aliasing 110.010s 447.536us 1 1 100.00
flash_ctrl_same_csr_outstanding 129.710s 898.693us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 112.830s 43.804us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 112.830s 43.804us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 112.830s 43.804us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 112.830s 43.804us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 128.080s 149.941us 1 1 100.00
tl_intg_err 1 2 50.00
flash_ctrl_sec_cm 10800.124s 0.000us 0 1 0.00
flash_ctrl_tl_intg_err 1678.330s 455.204us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 1678.330s 455.204us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 1678.330s 455.204us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 128.690s 79.222us 1 1 100.00
flash_ctrl_wr_intg 59.210s 51.835us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 257.000s 104.574us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 553.160s 86.579us 1 1 100.00
flash_ctrl_disable 133.280s 23.942us 1 1 100.00
flash_ctrl_sec_info_access 102.710s 3445.768us 1 1 100.00
flash_ctrl_connect 83.100s 50.022us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 101.780s 81.879us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 103.900s 42.048us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 112.830s 43.804us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 103.900s 42.048us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 112.830s 43.804us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 103.900s 42.048us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 112.830s 43.804us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 133.280s 23.942us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 128.690s 79.222us 1 1 100.00
flash_ctrl_access_after_disable 98.710s 76.242us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 153.970s 41.734us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 133.280s 23.942us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 110.870s 1091.072us 1 1 100.00
sec_cm_mem_scramble 0 1 0.00
flash_ctrl_rw 406.450s 7227.402us 0 1 0.00
sec_cm_mem_integrity 1 3 33.33
flash_ctrl_rw_serr 207.350s 3735.062us 1 1 100.00
flash_ctrl_rw_derr 2781.780s 200000.000us 0 1 0.00
flash_ctrl_integrity 232.000s 1487.690us 0 1 0.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1669.490s 85808.897us 1 1 100.00
sec_cm_ctrl_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 10800.124s 0.000us 0 1 0.00
sec_cm_phy_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 10800.124s 0.000us 0 1 0.00
sec_cm_phy_prog_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 10800.124s 0.000us 0 1 0.00
sec_cm_ctr_redun 0 1 0.00
flash_ctrl_sec_cm 10800.124s 0.000us 0 1 0.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 71.410s 915.001us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 61.390s 49.528us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 61.800s 44.022us 1 1 100.00
sec_cm_fifo_ctr_redun 0 1 0.00
flash_ctrl_sec_cm 10800.124s 0.000us 0 1 0.00
sec_cm_mem_tl_lc_gate_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 10800.124s 0.000us 0 1 0.00
sec_cm_prog_tl_lc_gate_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 10800.124s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 190.310s 272.886us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
flash_ctrl_basic_rw 3600.167s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 5 test runs
flash_ctrl_error_prog_type 36013369147109362341020572779322526143130281658694195317163890616429434280982 None
flash_ctrl_error_prog_win 108046583758179577726713613105352574167739792987316361458729188737675312524253 None
flash_ctrl_error_mp 83310600339908094239387919378539133950899466964474680924041242116624056491655 None
flash_ctrl_sec_cm 86964611210425156858026112248668027989900418539255832606856106043973102016890 None
flash_ctrl_basic_rw 50596555768914327053880891940314495775502670252844540610527720461799800931926 None
UVM_ERROR (flash_ctrl_scoreboard.sv:735) [scoreboard] Check failed exp_data_part[addr] == data (* [*] vs * [*]) read addr:* data: * 1 test run
flash_ctrl_full_mem_access 43527566161127041389085768555754758285034894553038122670685231095890252498813 275581
UVM_INFO @ 359049472.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly 1 test run
flash_ctrl_ro 81220277939269525909404218355206078733609543548075219823143325373312697291775 114
UVM_INFO @ 712168.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly 1 test run
flash_ctrl_rw 81438521905500220933562593693785802588482229520503750623913261858963972195735 114
UVM_INFO @ 7227402.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue 1 test run
flash_ctrl_rw_derr 44010168452928344836051953750704220930014008190643916671136409868133739461287 114
UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:573) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) 1 test run
flash_ctrl_integrity 22522236095210874399031256363907091863109299079051648597696762749710830546841 114
UVM_INFO @ 1487690.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---