Simulation Results: hmac

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 75.53 %
  • code
  • 86.90 %
  • assert
  • 97.60 %
  • func
  • 42.08 %
  • line
  • 99.64 %
  • branch
  • 98.86 %
  • cond
  • 95.69 %
  • toggle
  • 46.17 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 4.600s 5228.971us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.800s 33.246us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.920s 17.515us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 9.700s 2599.971us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.100s 991.741us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.240s 102.998us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.920s 17.515us 1 1 100.00
hmac_csr_aliasing 6.100s 991.741us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 33.270s 20125.915us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 86.530s 3158.324us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.160s 228.618us 1 1 100.00
hmac_test_sha384_vectors 369.120s 110791.771us 1 1 100.00
hmac_test_sha512_vectors 19.750s 1130.386us 1 1 100.00
hmac_test_hmac256_vectors 5.840s 228.002us 1 1 100.00
hmac_test_hmac384_vectors 7.530s 3596.964us 1 1 100.00
hmac_test_hmac512_vectors 12.210s 457.048us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 11.970s 1604.900us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 904.430s 11394.980us 1 1 100.00
error 1 1 100.00
hmac_error 5.270s 839.422us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 23.270s 12794.407us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 4.600s 5228.971us 1 1 100.00
hmac_long_msg 33.270s 20125.915us 1 1 100.00
hmac_back_pressure 86.530s 3158.324us 1 1 100.00
hmac_datapath_stress 904.430s 11394.980us 1 1 100.00
hmac_burst_wr 11.970s 1604.900us 1 1 100.00
hmac_stress_all 463.800s 51801.873us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 4.600s 5228.971us 1 1 100.00
hmac_long_msg 33.270s 20125.915us 1 1 100.00
hmac_back_pressure 86.530s 3158.324us 1 1 100.00
hmac_datapath_stress 904.430s 11394.980us 1 1 100.00
hmac_wipe_secret 23.270s 12794.407us 1 1 100.00
hmac_test_sha256_vectors 8.160s 228.618us 1 1 100.00
hmac_test_sha384_vectors 369.120s 110791.771us 1 1 100.00
hmac_test_sha512_vectors 19.750s 1130.386us 1 1 100.00
hmac_test_hmac256_vectors 5.840s 228.002us 1 1 100.00
hmac_test_hmac384_vectors 7.530s 3596.964us 1 1 100.00
hmac_test_hmac512_vectors 12.210s 457.048us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 4.600s 5228.971us 1 1 100.00
hmac_long_msg 33.270s 20125.915us 1 1 100.00
hmac_back_pressure 86.530s 3158.324us 1 1 100.00
hmac_datapath_stress 904.430s 11394.980us 1 1 100.00
hmac_burst_wr 11.970s 1604.900us 1 1 100.00
hmac_error 5.270s 839.422us 1 1 100.00
hmac_wipe_secret 23.270s 12794.407us 1 1 100.00
hmac_test_sha256_vectors 8.160s 228.618us 1 1 100.00
hmac_test_sha384_vectors 369.120s 110791.771us 1 1 100.00
hmac_test_sha512_vectors 19.750s 1130.386us 1 1 100.00
hmac_test_hmac256_vectors 5.840s 228.002us 1 1 100.00
hmac_test_hmac384_vectors 7.530s 3596.964us 1 1 100.00
hmac_test_hmac512_vectors 12.210s 457.048us 1 1 100.00
hmac_stress_all 463.800s 51801.873us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 463.800s 51801.873us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.660s 58.331us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.690s 26.928us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.410s 310.481us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.410s 310.481us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.800s 33.246us 1 1 100.00
hmac_csr_rw 0.920s 17.515us 1 1 100.00
hmac_csr_aliasing 6.100s 991.741us 1 1 100.00
hmac_same_csr_outstanding 1.220s 287.663us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.800s 33.246us 1 1 100.00
hmac_csr_rw 0.920s 17.515us 1 1 100.00
hmac_csr_aliasing 6.100s 991.741us 1 1 100.00
hmac_same_csr_outstanding 1.220s 287.663us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.810s 43.659us 1 1 100.00
hmac_tl_intg_err 1.940s 894.391us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.940s 894.391us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 4.600s 5228.971us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.070s 41.944us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 71.080s 10463.434us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.110s 169.671us 1 1 100.00