Simulation Results

Simulation Results: i2c

20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
86.61 %

code
78.66 %

assert
97.04 %

func
84.14 %

line
96.57 %

branch
92.62 %

cond
87.19 %

toggle
74.04 %

FSM
42.86 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	13.290s	15652.231us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	9.710s	2135.422us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.780s	24.762us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.680s	56.852us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.490s	1303.505us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.600s	357.929us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.120s	31.097us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.680s	56.852us	1	1	100.00
	i2c_csr_aliasing	1.600s	357.929us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.830s	38.397us	0	1	0.00
host_stress_all				1	1	100.00
	i2c_host_stress_all	1090.610s	67785.766us	1	1	100.00
host_maxperf				1	1	100.00
	i2c_host_perf	598.720s	49862.764us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.730s	68.873us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	41.840s	3605.317us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	68.920s	7815.164us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.110s	106.225us	1	1	100.00
	i2c_host_fifo_fmt_empty	5.700s	1076.726us	1	1	100.00
	i2c_host_fifo_reset_rx	4.290s	150.384us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	64.490s	7037.184us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	11.550s	890.973us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.750s	88.018us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.860s	933.583us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	52.320s	28508.530us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	2.500s	495.522us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	39.200s	5266.855us	1	1	100.00
	i2c_target_intr_smoke	3.480s	2563.705us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.400s	206.811us	1	1	100.00
	i2c_target_fifo_reset_tx	0.870s	288.075us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	317.110s	39377.258us	1	1	100.00
	i2c_target_stress_rd	39.200s	5266.855us	1	1	100.00
	i2c_target_intr_stress_wr	2.080s	7108.750us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	5.760s	6019.993us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	6.000s	2816.185us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.560s	943.631us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.650s	327.053us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.360s	2444.117us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.950s	151.379us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	598.720s	49862.764us	1	1	100.00
	i2c_host_perf_precise	67.510s	25177.313us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	11.550s	890.973us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.530s	274.226us	1	1	100.00
target_mode_nack_generation				2	3	66.67
	i2c_target_nack_acqfull	2.070s	673.771us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.050s	513.995us	1	1	100.00
	i2c_target_nack_txstretch	1.480s	896.433us	0	1	0.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	10.000s	458.140us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.650s	589.733us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.890s	30.355us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.700s	32.776us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.410s	252.310us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.410s	252.310us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.780s	24.762us	1	1	100.00
	i2c_csr_rw	0.680s	56.852us	1	1	100.00
	i2c_csr_aliasing	1.600s	357.929us	1	1	100.00
	i2c_same_csr_outstanding	1.270s	207.339us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.780s	24.762us	1	1	100.00
	i2c_csr_rw	0.680s	56.852us	1	1	100.00
	i2c_csr_aliasing	1.600s	357.929us	1	1	100.00
	i2c_same_csr_outstanding	1.270s	207.339us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.300s	130.803us	1	1	100.00
	i2c_sec_cm	1.020s	139.105us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.300s	130.803us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	2.320s	209.157us	1
target_error_intr				1
	i2c_target_unexp_stop	0.980s	128.560us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	10.220s	902.988us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1296) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	89037965088071309053319972870666215715986865578474289013295429219564420591268	90	UVM_INFO @ 209156735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	30083409166120332736145635030671878171008306595313017595886970296384809476923	94	UVM_INFO @ 902988100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				1 test run
	i2c_host_error_intr	46916052313840082466219986388364101329412525376746829613767406002688590537625	86	UVM_INFO @ 38397265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	27164790468118899109801995255127304538725725774856402778628977902531624856663	90	UVM_INFO @ 933582574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1382) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])				1 test run
	i2c_target_unexp_stop	22430921880782122321228178338296598101321914252038894468340739833421653593071	84	UVM_INFO @ 128560493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:625) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead				1 test run
	i2c_host_mode_toggle	102200250052611020520252986986004157540768089929674482312071051943404289016732	93	--> EXP: --------------------------------------------------- Name Type Size Value ---------------------------------------------------
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: i2c_reg_block.target_nack_count reset value:				1 test run
	i2c_target_nack_txstretch	88763535152242592725288699649417057722366088180595178712427397791019688808802	84	UVM_INFO @ 896433185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---