Simulation Results: keymgr_dpe/earlgrey

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 54.72 %
  • code
  • 60.20 %
  • assert
  • 95.10 %
  • func
  • 8.86 %
  • line
  • 92.47 %
  • branch
  • 83.13 %
  • cond
  • 74.20 %
  • toggle
  • 43.10 %
  • FSM
  • 8.11 %
Validation stages
V1
83.33%
V2
100.00%
V2S
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 1 0.00
keymgr_dpe_smoke 7.200s 588.663us 0 1 0.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 0.960s 33.603us 1 1 100.00
csr_rw 1 1 100.00
keymgr_dpe_csr_rw 0.990s 153.120us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 6.680s 2975.964us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 1.870s 181.267us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 0.940s 265.592us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_dpe_csr_rw 0.990s 153.120us 1 1 100.00
keymgr_dpe_csr_aliasing 1.870s 181.267us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 1 1 100.00
keymgr_dpe_intr_test 0.680s 9.751us 1 1 100.00
alert_test 1 1 100.00
keymgr_dpe_alert_test 0.750s 27.490us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_dpe_tl_errors 2.050s 362.683us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_dpe_tl_errors 2.050s 362.683us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_dpe_csr_hw_reset 0.960s 33.603us 1 1 100.00
keymgr_dpe_csr_rw 0.990s 153.120us 1 1 100.00
keymgr_dpe_csr_aliasing 1.870s 181.267us 1 1 100.00
keymgr_dpe_same_csr_outstanding 1.450s 158.662us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_dpe_csr_hw_reset 0.960s 33.603us 1 1 100.00
keymgr_dpe_csr_rw 0.990s 153.120us 1 1 100.00
keymgr_dpe_csr_aliasing 1.870s 181.267us 1 1 100.00
keymgr_dpe_same_csr_outstanding 1.450s 158.662us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
keymgr_dpe_sec_cm 6.090s 1338.745us 1 1 100.00
keymgr_dpe_tl_intg_err 3.010s 360.405us 1 1 100.00
shadow_reg_update_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 1.240s 61.568us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
keymgr_dpe_shadow_reg_errors 1.240s 61.568us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 1.240s 61.568us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
keymgr_dpe_shadow_reg_errors 1.240s 61.568us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 1.050s 28.549us 0 1 0.00
prim_count_check 1 1 100.00
keymgr_dpe_sec_cm 6.090s 1338.745us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_dpe_sec_cm 6.090s 1338.745us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (keymgr_dpe_scoreboard.sv:658) scoreboard [scoreboard] After a disable kmac sideload key was not presevedexp * vs. act * 1 test run
keymgr_dpe_smoke 77939691554180265764819117161517532074041895310557502310414840160084918042912 2631
UVM_INFO @ 588663448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(reg2hw.control_shadowed.slot_dst_sel.q < NumInstHwSlot)' 1 test run
keymgr_dpe_shadow_reg_errors 46071440502203727567704826173708716836072092229863516120318782878102274621549 83
UVM_ERROR @ 61568340 ps: (keymgr_dpe.sv:321) [ASSERT FAILED] DstSelInRange_A
UVM_INFO @ 61568340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(reg2hw.control_shadowed.slot_src_sel.q < NumInstHwSlot)' 1 test run
keymgr_dpe_shadow_reg_errors_with_csr_rw 4870864622514876594566272650783610186956391345329648911722498914531699777855 83
UVM_ERROR @ 28549038 ps: (keymgr_dpe.sv:320) [ASSERT FAILED] SrcSelInRange_A
UVM_INFO @ 28549038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---