Simulation Results: lc_ctrl/volatile_unlock_disabled

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 89.90 %
  • code
  • 83.02 %
  • assert
  • 93.85 %
  • func
  • 92.83 %
  • line
  • 97.15 %
  • branch
  • 93.47 %
  • cond
  • 78.89 %
  • toggle
  • 82.97 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.770s 47.425us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.860s 22.949us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.030s 27.785us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.310s 373.520us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 15.749us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.590s 26.572us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.030s 27.785us 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 15.749us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.240s 87.371us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.980s 395.867us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.060s 12.578us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.530s 218.687us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.440s 1176.728us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 3.390s 1034.865us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.440s 1176.728us 1 1 100.00
lc_ctrl_prog_failure 1.530s 218.687us 1 1 100.00
lc_ctrl_errors 3.390s 1034.865us 1 1 100.00
lc_ctrl_security_escalation 4.510s 319.062us 1 1 100.00
lc_ctrl_jtag_state_failure 20.710s 26954.827us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.870s 371.689us 1 1 100.00
lc_ctrl_jtag_errors 18.510s 14345.457us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.210s 299.266us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.760s 2417.555us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.870s 371.689us 1 1 100.00
lc_ctrl_jtag_errors 18.510s 14345.457us 1 1 100.00
lc_ctrl_jtag_access 1.610s 232.586us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.110s 3166.200us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.840s 410.224us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.150s 819.732us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.670s 2250.949us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.420s 786.587us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.000s 21.723us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.880s 197.589us 1 1 100.00
lc_ctrl_jtag_alert_test 1.250s 96.975us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.930s 966.990us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.870s 19.680us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 155.940s 50144.356us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 25.445us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.630s 1180.478us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.630s 1180.478us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.860s 22.949us 1 1 100.00
lc_ctrl_csr_rw 1.030s 27.785us 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 15.749us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.620s 44.886us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.860s 22.949us 1 1 100.00
lc_ctrl_csr_rw 1.030s 27.785us 1 1 100.00
lc_ctrl_csr_aliasing 1.050s 15.749us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.620s 44.886us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.350s 336.816us 1 1 100.00
lc_ctrl_tl_intg_err 1.150s 282.258us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.150s 282.258us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.980s 395.867us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.440s 1176.728us 1 1 100.00
lc_ctrl_sec_cm 6.350s 336.816us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.440s 1176.728us 1 1 100.00
lc_ctrl_sec_cm 6.350s 336.816us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.440s 1176.728us 1 1 100.00
lc_ctrl_sec_cm 6.350s 336.816us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.440s 1176.728us 1 1 100.00
lc_ctrl_sec_cm 6.350s 336.816us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.440s 1176.728us 1 1 100.00
lc_ctrl_sec_cm 6.350s 336.816us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.440s 1176.728us 1 1 100.00
lc_ctrl_sec_cm 6.350s 336.816us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.440s 1176.728us 1 1 100.00
lc_ctrl_sec_cm 6.350s 336.816us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.440s 1176.728us 1 1 100.00
lc_ctrl_sec_cm 6.350s 336.816us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.510s 319.062us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.240s 87.371us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.760s 2417.555us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.090s 1132.850us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.090s 1132.850us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.980s 950.723us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.090s 470.014us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.090s 470.014us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 20.670s 5417.440us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_stress_all 2753793873785051970106513386714379912926637692612395843015746440510377678701 14228
UVM_INFO @ 50144355572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 91502463367417882516242186419888274968514867438362395390229862361282672056926 2951
UVM_INFO @ 5417440435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---