Simulation Results: lc_ctrl/volatile_unlock_enabled

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.40 %
  • code
  • 84.05 %
  • assert
  • 94.13 %
  • func
  • 93.01 %
  • line
  • 97.26 %
  • branch
  • 93.86 %
  • cond
  • 79.90 %
  • toggle
  • 85.68 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.830s 44.633us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.780s 21.779us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.810s 63.743us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.250s 55.774us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.920s 27.750us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.890s 26.069us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.810s 63.743us 1 1 100.00
lc_ctrl_csr_aliasing 0.920s 27.750us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 1.800s 106.927us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.960s 357.112us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.680s 35.537us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.870s 354.175us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.820s 348.500us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 3.100s 2591.249us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.820s 348.500us 1 1 100.00
lc_ctrl_prog_failure 1.870s 354.175us 1 1 100.00
lc_ctrl_errors 3.100s 2591.249us 1 1 100.00
lc_ctrl_security_escalation 3.180s 227.822us 1 1 100.00
lc_ctrl_jtag_state_failure 28.640s 21652.484us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.240s 9015.865us 1 1 100.00
lc_ctrl_jtag_errors 11.740s 4729.016us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.840s 3529.803us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.850s 1146.652us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.240s 9015.865us 1 1 100.00
lc_ctrl_jtag_errors 11.740s 4729.016us 1 1 100.00
lc_ctrl_jtag_access 4.610s 2311.317us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.330s 4508.155us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.760s 583.011us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.960s 175.516us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.080s 673.508us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.480s 632.457us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.380s 54.379us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.500s 303.472us 1 1 100.00
lc_ctrl_jtag_alert_test 0.790s 26.990us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.270s 575.171us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.770s 14.897us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 48.510s 15177.307us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.790s 26.024us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.130s 143.699us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.130s 143.699us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.780s 21.779us 1 1 100.00
lc_ctrl_csr_rw 0.810s 63.743us 1 1 100.00
lc_ctrl_csr_aliasing 0.920s 27.750us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.150s 22.780us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.780s 21.779us 1 1 100.00
lc_ctrl_csr_rw 0.810s 63.743us 1 1 100.00
lc_ctrl_csr_aliasing 0.920s 27.750us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.150s 22.780us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.940s 1047.034us 1 1 100.00
lc_ctrl_tl_intg_err 2.150s 122.068us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.150s 122.068us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.960s 357.112us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.820s 348.500us 1 1 100.00
lc_ctrl_sec_cm 5.940s 1047.034us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.820s 348.500us 1 1 100.00
lc_ctrl_sec_cm 5.940s 1047.034us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.820s 348.500us 1 1 100.00
lc_ctrl_sec_cm 5.940s 1047.034us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.820s 348.500us 1 1 100.00
lc_ctrl_sec_cm 5.940s 1047.034us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.820s 348.500us 1 1 100.00
lc_ctrl_sec_cm 5.940s 1047.034us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.820s 348.500us 1 1 100.00
lc_ctrl_sec_cm 5.940s 1047.034us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.820s 348.500us 1 1 100.00
lc_ctrl_sec_cm 5.940s 1047.034us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.820s 348.500us 1 1 100.00
lc_ctrl_sec_cm 5.940s 1047.034us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.180s 227.822us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 1.800s 106.927us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.850s 1146.652us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.160s 679.540us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.160s 679.540us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 3.890s 331.351us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.410s 398.846us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.410s 398.846us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 18.360s 6490.117us 1 1 100.00