| V1 |
|
88.89% |
| V2 |
|
95.00% |
| V2S |
|
88.89% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 1 | 1 | 100.00 | |||
| otp_ctrl_wake_up | 1.450s | 200.365us | 1 | 1 | 100.00 | |
| smoke | 1 | 1 | 100.00 | |||
| otp_ctrl_smoke | 17.030s | 8072.253us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| otp_ctrl_csr_hw_reset | 1.670s | 1077.700us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| otp_ctrl_csr_rw | 1.320s | 43.139us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| otp_ctrl_csr_bit_bash | 8.100s | 608.671us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| otp_ctrl_csr_aliasing | 3.350s | 1716.045us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| otp_ctrl_csr_mem_rw_with_rand_reset | 1.160s | 111.031us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| otp_ctrl_csr_rw | 1.320s | 43.139us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_aliasing | 3.350s | 1716.045us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| otp_ctrl_mem_walk | 1.150s | 40.695us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| otp_ctrl_mem_partial_access | 1.260s | 121.671us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dai_access_partition_walk | 1 | 1 | 100.00 | |||
| otp_ctrl_partition_walk | 14.110s | 741.556us | 1 | 1 | 100.00 | |
| init_fail | 1 | 1 | 100.00 | |||
| otp_ctrl_init_fail | 2.540s | 486.801us | 1 | 1 | 100.00 | |
| partition_check | 1 | 2 | 50.00 | |||
| otp_ctrl_background_chks | 19.950s | 2303.764us | 1 | 1 | 100.00 | |
| otp_ctrl_check_fail | 6.190s | 520.500us | 0 | 1 | 0.00 | |
| regwen_during_otp_init | 1 | 1 | 100.00 | |||
| otp_ctrl_regwen | 4.110s | 161.107us | 1 | 1 | 100.00 | |
| partition_lock | 1 | 1 | 100.00 | |||
| otp_ctrl_dai_lock | 12.010s | 1834.248us | 1 | 1 | 100.00 | |
| interface_key_check | 1 | 1 | 100.00 | |||
| otp_ctrl_parallel_key_req | 3.580s | 389.255us | 1 | 1 | 100.00 | |
| lc_interactions | 2 | 2 | 100.00 | |||
| otp_ctrl_parallel_lc_req | 5.500s | 256.542us | 1 | 1 | 100.00 | |
| otp_ctrl_parallel_lc_esc | 7.300s | 1268.208us | 1 | 1 | 100.00 | |
| otp_dai_errors | 1 | 1 | 100.00 | |||
| otp_ctrl_dai_errs | 11.780s | 2157.429us | 1 | 1 | 100.00 | |
| otp_macro_errors | 1 | 1 | 100.00 | |||
| otp_ctrl_macro_errs | 3.850s | 800.106us | 1 | 1 | 100.00 | |
| test_access | 1 | 1 | 100.00 | |||
| otp_ctrl_test_access | 16.780s | 1886.608us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| otp_ctrl_stress_all | 210.040s | 77739.962us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| otp_ctrl_intr_test | 1.190s | 39.676us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| otp_ctrl_alert_test | 2.090s | 134.115us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| otp_ctrl_tl_errors | 3.830s | 437.677us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| otp_ctrl_tl_errors | 3.830s | 437.677us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| otp_ctrl_csr_hw_reset | 1.670s | 1077.700us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_rw | 1.320s | 43.139us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_aliasing | 3.350s | 1716.045us | 1 | 1 | 100.00 | |
| otp_ctrl_same_csr_outstanding | 2.270s | 190.633us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| otp_ctrl_csr_hw_reset | 1.670s | 1077.700us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_rw | 1.320s | 43.139us | 1 | 1 | 100.00 | |
| otp_ctrl_csr_aliasing | 3.350s | 1716.045us | 1 | 1 | 100.00 | |
| otp_ctrl_same_csr_outstanding | 2.270s | 190.633us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| sec_cm_additional_check | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| otp_ctrl_tl_intg_err | 6.590s | 704.571us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| prim_fsm_check | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| otp_ctrl_tl_intg_err | 6.590s | 704.571us | 1 | 1 | 100.00 | |
| sec_cm_secret_mem_scramble | 1 | 1 | 100.00 | |||
| otp_ctrl_smoke | 17.030s | 8072.253us | 1 | 1 | 100.00 | |
| sec_cm_part_mem_digest | 1 | 1 | 100.00 | |||
| otp_ctrl_smoke | 17.030s | 8072.253us | 1 | 1 | 100.00 | |
| sec_cm_dai_fsm_sparse | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| sec_cm_kdi_fsm_sparse | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| sec_cm_lci_fsm_sparse | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| sec_cm_part_fsm_sparse | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| sec_cm_scrmbl_fsm_sparse | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| sec_cm_timer_fsm_sparse | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| sec_cm_dai_ctr_redun | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| sec_cm_kdi_seed_ctr_redun | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| sec_cm_kdi_entropy_ctr_redun | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| sec_cm_lci_ctr_redun | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| sec_cm_part_ctr_redun | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| sec_cm_scrmbl_ctr_redun | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| sec_cm_timer_integ_ctr_redun | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| sec_cm_timer_cnsty_ctr_redun | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| sec_cm_timer_lfsr_redun | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| sec_cm_dai_fsm_local_esc | 2 | 2 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 7.300s | 1268.208us | 1 | 1 | 100.00 | |
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| sec_cm_lci_fsm_local_esc | 1 | 1 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 7.300s | 1268.208us | 1 | 1 | 100.00 | |
| sec_cm_kdi_fsm_local_esc | 1 | 1 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 7.300s | 1268.208us | 1 | 1 | 100.00 | |
| sec_cm_part_fsm_local_esc | 2 | 2 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 7.300s | 1268.208us | 1 | 1 | 100.00 | |
| otp_ctrl_macro_errs | 3.850s | 800.106us | 1 | 1 | 100.00 | |
| sec_cm_scrmbl_fsm_local_esc | 1 | 1 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 7.300s | 1268.208us | 1 | 1 | 100.00 | |
| sec_cm_timer_fsm_local_esc | 2 | 2 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 7.300s | 1268.208us | 1 | 1 | 100.00 | |
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| sec_cm_dai_fsm_global_esc | 2 | 2 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 7.300s | 1268.208us | 1 | 1 | 100.00 | |
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| sec_cm_lci_fsm_global_esc | 1 | 1 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 7.300s | 1268.208us | 1 | 1 | 100.00 | |
| sec_cm_kdi_fsm_global_esc | 1 | 1 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 7.300s | 1268.208us | 1 | 1 | 100.00 | |
| sec_cm_part_fsm_global_esc | 2 | 2 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 7.300s | 1268.208us | 1 | 1 | 100.00 | |
| otp_ctrl_macro_errs | 3.850s | 800.106us | 1 | 1 | 100.00 | |
| sec_cm_scrmbl_fsm_global_esc | 1 | 1 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 7.300s | 1268.208us | 1 | 1 | 100.00 | |
| sec_cm_timer_fsm_global_esc | 2 | 2 | 100.00 | |||
| otp_ctrl_parallel_lc_esc | 7.300s | 1268.208us | 1 | 1 | 100.00 | |
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| sec_cm_part_data_reg_integrity | 1 | 1 | 100.00 | |||
| otp_ctrl_init_fail | 2.540s | 486.801us | 1 | 1 | 100.00 | |
| sec_cm_part_data_reg_bkgn_chk | 0 | 1 | 0.00 | |||
| otp_ctrl_check_fail | 6.190s | 520.500us | 0 | 1 | 0.00 | |
| sec_cm_part_mem_regren | 1 | 1 | 100.00 | |||
| otp_ctrl_dai_lock | 12.010s | 1834.248us | 1 | 1 | 100.00 | |
| sec_cm_part_mem_sw_unreadable | 1 | 1 | 100.00 | |||
| otp_ctrl_dai_lock | 12.010s | 1834.248us | 1 | 1 | 100.00 | |
| sec_cm_part_mem_sw_unwritable | 1 | 1 | 100.00 | |||
| otp_ctrl_dai_lock | 12.010s | 1834.248us | 1 | 1 | 100.00 | |
| sec_cm_lc_part_mem_sw_noaccess | 1 | 1 | 100.00 | |||
| otp_ctrl_dai_lock | 12.010s | 1834.248us | 1 | 1 | 100.00 | |
| sec_cm_access_ctrl_mubi | 1 | 1 | 100.00 | |||
| otp_ctrl_dai_lock | 12.010s | 1834.248us | 1 | 1 | 100.00 | |
| sec_cm_token_valid_ctrl_mubi | 1 | 1 | 100.00 | |||
| otp_ctrl_smoke | 17.030s | 8072.253us | 1 | 1 | 100.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 1 | 1 | 100.00 | |||
| otp_ctrl_dai_lock | 12.010s | 1834.248us | 1 | 1 | 100.00 | |
| sec_cm_test_bus_lc_gated | 1 | 1 | 100.00 | |||
| otp_ctrl_smoke | 17.030s | 8072.253us | 1 | 1 | 100.00 | |
| sec_cm_test_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| otp_ctrl_sec_cm | 116.930s | 11076.334us | 1 | 1 | 100.00 | |
| sec_cm_direct_access_config_regwen | 1 | 1 | 100.00 | |||
| otp_ctrl_regwen | 4.110s | 161.107us | 1 | 1 | 100.00 | |
| sec_cm_check_trigger_config_regwen | 1 | 1 | 100.00 | |||
| otp_ctrl_smoke | 17.030s | 8072.253us | 1 | 1 | 100.00 | |
| sec_cm_check_config_regwen | 1 | 1 | 100.00 | |||
| otp_ctrl_smoke | 17.030s | 8072.253us | 1 | 1 | 100.00 | |
| sec_cm_macro_mem_integrity | 1 | 1 | 100.00 | |||
| otp_ctrl_macro_errs | 3.850s | 800.106us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| otp_ctrl_low_freq_read | 1 | 1 | 100.00 | |||
| otp_ctrl_low_freq_read | 11.350s | 8000.377us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| otp_ctrl_stress_all_with_rand_reset | 17.180s | 1710.369us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* | 1 test run | |||
| otp_ctrl_check_fail | 32537802759861491062829472936320194956075134847270917349155184376423542179715 | 7285 |
UVM_INFO @ 520500451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state | 1 test run | |||
| otp_ctrl_stress_all_with_rand_reset | 53598076214648492301539299110462356287753980298226813409357870474735437934458 | 3744 |
UVM_INFO @ 1710368888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_scoreboard.sv:764) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * | 1 test run | |||
| otp_ctrl_csr_mem_rw_with_rand_reset | 47190509373407531803499262087632300888404337156045828862454147407656023412375 | 98 |
UVM_INFO @ 111031224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|