Simulation Results: pwrmgr

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 96.07 %
  • code
  • 94.55 %
  • assert
  • 97.13 %
  • func
  • 96.54 %
  • line
  • 98.93 %
  • branch
  • 95.62 %
  • cond
  • 94.20 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
83.33%
V2
86.67%
V2S
72.73%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.860s 24.481us 1 1 100.00
csr_hw_reset 0 1 0.00
pwrmgr_csr_hw_reset 3600.028s 0.000us 0 1 0.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.670s 81.173us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.650s 192.743us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.900s 170.408us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.880s 54.285us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.670s 81.173us 1 1 100.00
pwrmgr_csr_aliasing 0.900s 170.408us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.810s 71.545us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.810s 71.545us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.940s 37.714us 1 1 100.00
pwrmgr_lowpower_invalid 0.650s 77.832us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 0.900s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.850s 102.012us 1 1 100.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 0.900s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.920s 140.148us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 1.040s 154.395us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.880s 154.692us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 4.350s 2501.596us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.740s 57.497us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.340s 297.948us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.340s 297.948us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
pwrmgr_csr_hw_reset 3600.028s 0.000us 0 1 0.00
pwrmgr_csr_rw 0.670s 81.173us 1 1 100.00
pwrmgr_csr_aliasing 0.900s 170.408us 1 1 100.00
pwrmgr_same_csr_outstanding 0.870s 43.677us 1 1 100.00
tl_d_partial_access 3 4 75.00
pwrmgr_csr_hw_reset 3600.028s 0.000us 0 1 0.00
pwrmgr_csr_rw 0.670s 81.173us 1 1 100.00
pwrmgr_csr_aliasing 0.900s 170.408us 1 1 100.00
pwrmgr_same_csr_outstanding 0.870s 43.677us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 3600.023s 0.000us 0 1 0.00
pwrmgr_sec_cm 3600.034s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 3600.034s 0.000us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 3600.034s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 3600.023s 0.000us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.750s 991.427us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.920s 140.148us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.510s 1474.881us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.760s 432.845us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.700s 39.502us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 3600.034s 0.000us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 3600.034s 0.000us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 3600.034s 0.000us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.650s 26.050us 1 1 100.00
sec_cm_main_pd_rst_local_esc 0 1 0.00
pwrmgr_glitch 3600.030s 0.000us 0 1 0.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.840s 119.748us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.670s 81.173us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.670s 81.173us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.730s 374.766us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
pwrmgr_stress_all_with_rand_reset 3600.025s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 5 test runs
pwrmgr_glitch 11459770406919414130038906959868054455068080647848455918587115839940614347995 None
pwrmgr_tl_intg_err 86884422774271431172625194744032715907731532415674033427964743919653382107503 None
pwrmgr_sec_cm 27378394307929838734417226411413559904881744779082498569672932061297617354965 None
pwrmgr_stress_all_with_rand_reset 7685775156632089685675694567347843932280550771721968159717373370003854400392 None
pwrmgr_csr_hw_reset 46776763314376473568786738850918175075592118184756366570306930937964766285188 None
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_reset 70677247521677581335463393162127576730829997440325433262720479441927694886659 132
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---