Simulation Results: rom_ctrl/32kb

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 96.22 %
  • code
  • 94.12 %
  • assert
  • 97.68 %
  • func
  • 96.87 %
  • line
  • 98.94 %
  • branch
  • 98.55 %
  • cond
  • 97.77 %
  • toggle
  • 95.33 %
  • FSM
  • 80.00 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.250s 726.417us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 2.800s 66.341us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 1.900s 64.427us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.310s 128.464us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 1.780s 88.670us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 2.760s 55.253us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 1.900s 64.427us 1 1 100.00
rom_ctrl_csr_aliasing 1.780s 88.670us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 1.820s 50.638us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 1.700s 65.029us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 2.900s 229.356us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 13.580s 770.546us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 3.890s 718.748us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.140s 69.127us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.100s 209.461us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.100s 209.461us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 2.800s 66.341us 1 1 100.00
rom_ctrl_csr_rw 1.900s 64.427us 1 1 100.00
rom_ctrl_csr_aliasing 1.780s 88.670us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.630s 72.615us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 2.800s 66.341us 1 1 100.00
rom_ctrl_csr_rw 1.900s 64.427us 1 1 100.00
rom_ctrl_csr_aliasing 1.780s 88.670us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.630s 72.615us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 64.140s 16009.780us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.610s 731.155us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 100.580s 440.808us 1 1 100.00
rom_ctrl_tl_intg_err 42.350s 677.711us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 100.580s 440.808us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 100.580s 440.808us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 64.140s 16009.780us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 64.140s 16009.780us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 64.140s 16009.780us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 64.140s 16009.780us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 64.140s 16009.780us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 100.580s 440.808us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 100.580s 440.808us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.250s 726.417us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.250s 726.417us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.250s 726.417us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 42.350s 677.711us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 64.140s 16009.780us 1 1 100.00
rom_ctrl_kmac_err_chk 3.890s 718.748us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 64.140s 16009.780us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 64.140s 16009.780us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 64.140s 16009.780us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.610s 731.155us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 100.580s 440.808us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 160.750s 15337.206us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 88475649837546850960726115955597589358104597775577416679867834695154120311653 85
UVM_INFO @ 229356009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---