Simulation Results: rom_ctrl/64kb

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 95.74 %
  • code
  • 92.78 %
  • assert
  • 97.10 %
  • func
  • 97.35 %
  • line
  • 98.94 %
  • branch
  • 98.55 %
  • cond
  • 97.77 %
  • toggle
  • 95.29 %
  • FSM
  • 73.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.190s 788.167us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.620s 62.280us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.460s 62.607us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.610s 138.930us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.930s 53.103us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.420s 126.268us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.460s 62.607us 1 1 100.00
rom_ctrl_csr_aliasing 3.930s 53.103us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.880s 70.901us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.430s 56.559us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 5.680s 652.643us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 13.840s 152.885us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.300s 708.415us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.860s 51.939us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.680s 739.364us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.680s 739.364us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.620s 62.280us 1 1 100.00
rom_ctrl_csr_rw 3.460s 62.607us 1 1 100.00
rom_ctrl_csr_aliasing 3.930s 53.103us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.700s 64.579us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.620s 62.280us 1 1 100.00
rom_ctrl_csr_rw 3.460s 62.607us 1 1 100.00
rom_ctrl_csr_aliasing 3.930s 53.103us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.700s 64.579us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 99.630s 10612.088us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 15.580s 134.395us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 444.200s 6314.602us 1 1 100.00
rom_ctrl_tl_intg_err 53.010s 385.685us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 444.200s 6314.602us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 444.200s 6314.602us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 99.630s 10612.088us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 99.630s 10612.088us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 99.630s 10612.088us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 99.630s 10612.088us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 99.630s 10612.088us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 444.200s 6314.602us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 444.200s 6314.602us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.190s 788.167us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.190s 788.167us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.190s 788.167us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 53.010s 385.685us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 99.630s 10612.088us 1 1 100.00
rom_ctrl_kmac_err_chk 13.300s 708.415us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 99.630s 10612.088us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 99.630s 10612.088us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 99.630s 10612.088us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 15.580s 134.395us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 444.200s 6314.602us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 120.010s 9686.711us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 53570736989087162897533740258462485789074173593439620717783402301093060750810 85
UVM_INFO @ 652642948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---