Simulation Results: rstmgr

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 97.76 %
  • code
  • 99.10 %
  • assert
  • 98.66 %
  • func
  • 95.52 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.06 %
  • toggle
  • 98.99 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.260s 293.071us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.190s 143.332us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.040s 73.324us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.460s 702.870us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.600s 103.689us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.120s 124.653us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.040s 73.324us 1 1 100.00
rstmgr_csr_aliasing 1.600s 103.689us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.930s 94.622us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.160s 140.079us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.190s 179.653us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.910s 1053.406us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.910s 1053.406us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.910s 1053.406us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.910s 1053.406us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 22.260s 6753.543us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.090s 88.857us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.540s 145.244us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.540s 145.244us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.190s 143.332us 1 1 100.00
rstmgr_csr_rw 1.040s 73.324us 1 1 100.00
rstmgr_csr_aliasing 1.600s 103.689us 1 1 100.00
rstmgr_same_csr_outstanding 1.070s 106.157us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.190s 143.332us 1 1 100.00
rstmgr_csr_rw 1.040s 73.324us 1 1 100.00
rstmgr_csr_aliasing 1.600s 103.689us 1 1 100.00
rstmgr_same_csr_outstanding 1.070s 106.157us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 23.180s 16899.532us 1 1 100.00
rstmgr_tl_intg_err 3.790s 987.089us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 23.180s 16899.532us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 23.180s 16899.532us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 3.790s 987.089us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.310s 190.940us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 8.470s 2812.850us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.410s 304.209us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 23.180s 16899.532us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.040s 73.324us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.040s 73.324us 1 1 100.00