Simulation Results: rv_timer

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 96.12 %
  • code
  • 94.66 %
  • assert
  • 98.41 %
  • func
  • 95.29 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.690s 74.264us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.800s 45.858us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.630s 40.383us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.420s 192.102us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.880s 337.416us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.830s 18.744us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.630s 40.383us 1 1 100.00
rv_timer_csr_aliasing 0.880s 337.416us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 9.100s 9584.882us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 2.800s 1383.374us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 0.750s 50.393us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 0.750s 50.393us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.510s 5759.280us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.570s 41.667us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.560s 36.604us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.300s 143.432us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.300s 143.432us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.800s 45.858us 1 1 100.00
rv_timer_csr_rw 0.630s 40.383us 1 1 100.00
rv_timer_csr_aliasing 0.880s 337.416us 1 1 100.00
rv_timer_same_csr_outstanding 0.750s 15.086us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.800s 45.858us 1 1 100.00
rv_timer_csr_rw 0.630s 40.383us 1 1 100.00
rv_timer_csr_aliasing 0.880s 337.416us 1 1 100.00
rv_timer_same_csr_outstanding 0.750s 15.086us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.850s 86.234us 1 1 100.00
rv_timer_tl_intg_err 1.120s 369.755us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.120s 369.755us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 52.092us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.800s 840.374us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 23.690s 4627.680us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:179) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 60524651000279436508053062670964370321648072209631536094520133928064244145896 81
UVM_INFO @ 52092183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 10006738028316398670339701296133389529719556269127398812592557447274421465220 81
UVM_INFO @ 840374356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---