Simulation Results: spi_device/1r1w

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 85.93 %
  • code
  • 91.17 %
  • assert
  • 95.40 %
  • func
  • 71.23 %
  • line
  • 98.83 %
  • branch
  • 98.08 %
  • cond
  • 95.44 %
  • toggle
  • 74.14 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 27.140s 20045.638us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.960s 37.857us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.110s 57.420us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 18.340s 2318.036us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 7.160s 764.062us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.140s 424.122us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.110s 57.420us 1 1 100.00
spi_device_csr_aliasing 7.160s 764.062us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.810s 65.318us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.180s 72.428us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.860s 58.300us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.820s 2.827us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.990s 3.392us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.080s 80.334us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.080s 80.334us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 11.410s 22783.082us 1 1 100.00
spi_device_tpm_sts_read 0.820s 32.360us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 8.480s 1430.357us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 4.550s 1089.598us 1 1 100.00
spi_device_flash_all 251.240s 122841.052us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 6.850s 562.858us 1 1 100.00
spi_device_flash_all 251.240s 122841.052us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 6.850s 562.858us 1 1 100.00
spi_device_flash_all 251.240s 122841.052us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 251.240s 122841.052us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 8.820s 2898.963us 1 1 100.00
spi_device_flash_all 251.240s 122841.052us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 8.820s 2898.963us 1 1 100.00
spi_device_flash_all 251.240s 122841.052us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 8.820s 2898.963us 1 1 100.00
spi_device_flash_all 251.240s 122841.052us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 8.820s 2898.963us 1 1 100.00
spi_device_flash_all 251.240s 122841.052us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 8.820s 2898.963us 1 1 100.00
spi_device_flash_all 251.240s 122841.052us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.940s 341.666us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 60.930s 37796.672us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 60.930s 37796.672us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 60.930s 37796.672us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 12.860s 2981.452us 1 1 100.00
spi_device_read_buffer_direct 3.670s 3014.349us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 60.930s 37796.672us 1 1 100.00
spi_device_flash_all 251.240s 122841.052us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 251.240s 122841.052us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 251.240s 122841.052us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.030s 93.199us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.030s 93.199us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 33.380s 12057.779us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 27.140s 20045.638us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 260.820s 167639.520us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 56.100s 7283.853us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.870s 11.723us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.710s 20.627us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.930s 341.067us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.930s 341.067us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.960s 37.857us 1 1 100.00
spi_device_csr_rw 1.110s 57.420us 1 1 100.00
spi_device_csr_aliasing 7.160s 764.062us 1 1 100.00
spi_device_same_csr_outstanding 2.960s 308.495us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.960s 37.857us 1 1 100.00
spi_device_csr_rw 1.110s 57.420us 1 1 100.00
spi_device_csr_aliasing 7.160s 764.062us 1 1 100.00
spi_device_same_csr_outstanding 2.960s 308.495us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.210s 71.529us 1 1 100.00
spi_device_tl_intg_err 9.950s 1251.326us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 9.950s 1251.326us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1661) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 38789423307248095593163613983141962576512693075072933157230871863008280358991 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 2027008 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 2027008 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[902])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 74886638819535286588950113365662329257099232770099159625833730344332381101537 76
UVM_ERROR @ 1178177 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x71 [1110001] vs 0x0 [0])
UVM_ERROR @ 1272177 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3fd [1111111101] vs 0x0 [0])
UVM_ERROR @ 1338177 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5 [101] vs 0x0 [0])
UVM_ERROR @ 1339177 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1b7 [110110111] vs 0x0 [0])