Simulation Results: spi_host

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.32 %
  • code
  • 91.30 %
  • assert
  • 95.27 %
  • func
  • 87.39 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 14.000s 278.307us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 40.979us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 34.930us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 595.364us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 9.000s 45.635us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 621.803us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 34.930us 1 1 100.00
spi_host_csr_aliasing 9.000s 45.635us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 37.655us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 16.301us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 9.000s 209.602us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 9.000s 33.257us 1 1 100.00
spi_host_error_cmd 9.000s 18.179us 1 1 100.00
spi_host_event 14.000s 794.350us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 10.000s 435.784us 1 1 100.00
speed 1 1 100.00
spi_host_speed 10.000s 435.784us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 10.000s 435.784us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 13.000s 426.236us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 10.000s 81.594us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 9.000s 103.058us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 10.000s 435.784us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 10.000s 435.784us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 14.000s 278.307us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 14.000s 278.307us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 10.000s 301.676us 1 1 100.00
spien 1 1 100.00
spi_host_spien 10.000s 352.171us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 29.000s 4665.399us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 9.000s 110.868us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 9.000s 33.257us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 9.000s 15.586us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 16.681us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 77.200us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 77.200us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 40.979us 1 1 100.00
spi_host_csr_rw 1.000s 34.930us 1 1 100.00
spi_host_csr_aliasing 9.000s 45.635us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 24.443us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 40.979us 1 1 100.00
spi_host_csr_rw 1.000s 34.930us 1 1 100.00
spi_host_csr_aliasing 9.000s 45.635us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 24.443us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 800.304us 1 1 100.00
spi_host_sec_cm 9.000s 263.806us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 800.304us 1 1 100.00