Simulation Results: sram_ctrl/main

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.55 %
  • code
  • 95.09 %
  • assert
  • 97.55 %
  • func
  • 94.00 %
  • block
  • 94.48 %
  • line
  • 95.64 %
  • branch
  • 92.86 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 8.000s 704.367us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 21.276us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.567us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 36.480us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 63.111us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 723.559us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 20.567us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 63.111us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 435.000s 429604.591us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 78.000s 2752.974us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 14.000s 1718.834us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 84.000s 4233.789us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 207.000s 15792.476us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 65.000s 9133.931us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 76.000s 95349.969us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 42.000s 23145.223us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 1389.290us 1 1 100.00
sram_ctrl_partial_access_b2b 236.000s 12872.757us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 6.000s 1331.942us 1 1 100.00
sram_ctrl_throughput_w_partial_write 6.000s 685.189us 1 1 100.00
sram_ctrl_throughput_w_readback 12.000s 2678.954us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 11.000s 1510.113us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 365.351us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 352.000s 224874.900us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 57.392us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 104.470us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 104.470us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 21.276us 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.567us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 63.111us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 46.338us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 21.276us 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.567us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 63.111us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 46.338us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.000s 37034.139us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 6.000s 891.493us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 296.199us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 6.000s 891.493us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 296.199us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 1510.113us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 1510.113us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.567us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 42.000s 23145.223us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 42.000s 23145.223us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 42.000s 23145.223us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 76.000s 95349.969us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3602.112s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.000s 37034.139us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3602.123s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 8.000s 704.367us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 8.000s 704.367us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 42.000s 23145.223us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 6.000s 891.493us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 76.000s 95349.969us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 6.000s 891.493us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 6.000s 891.493us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 8.000s 704.367us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 6.000s 891.493us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 10.000s 546.515us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 73798624797067127608658016184815410672999975334570117648347004966248300197495 None
sram_ctrl_mubi_enc_err 83316089953152686798289258907392278036483514319134675394316425675813261343169 None