Simulation Results: sram_ctrl/ret

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.20 %
  • code
  • 81.75 %
  • assert
  • 97.26 %
  • func
  • 91.60 %
  • block
  • 92.19 %
  • line
  • 93.78 %
  • branch
  • 88.23 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 203.738us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 16.358us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.907us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 262.888us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.946us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 61.963us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 18.907us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.946us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 6.000s 364.733us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 5.000s 191.155us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 16.000s 1038.958us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 157.000s 8295.818us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 7.000s 219.136us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 23.000s 2693.958us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 4.000s 1139.447us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 9.000s 593.916us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 51.175us 1 1 100.00
sram_ctrl_partial_access_b2b 154.000s 2843.441us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 126.790us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 42.113us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 140.754us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 3.000s 703.312us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 71.611us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 67.000s 18916.079us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 21.534us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 118.125us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 118.125us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.358us 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.907us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.946us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 74.930us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.358us 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.907us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.946us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 74.930us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 506.174us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 426.240us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 403.982us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 426.240us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 403.982us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 703.312us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 703.312us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.907us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 9.000s 593.916us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 593.916us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 593.916us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 4.000s 1139.447us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3601.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 506.174us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 203.738us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 203.738us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 9.000s 593.916us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 426.240us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 4.000s 1139.447us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 426.240us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 426.240us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 203.738us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 426.240us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 27.000s 7099.084us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 61317548200114696057949985789824133762274110084730967274639472863857051142028 None
sram_ctrl_mubi_enc_err 84724492580643575801436417232639736569448554748036295869429093079848888633297 None