| V1 |
|
100.00% |
| V2 |
|
94.44% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| sysrst_ctrl_smoke | 1.940s | 2121.928us | 1 | 1 | 100.00 | |
| input_output_inverted | 1 | 1 | 100.00 | |||
| sysrst_ctrl_in_out_inverted | 1.950s | 2464.980us | 1 | 1 | 100.00 | |
| combo_detect_ec_rst | 1 | 1 | 100.00 | |||
| sysrst_ctrl_combo_detect_ec_rst | 3.160s | 2189.016us | 1 | 1 | 100.00 | |
| combo_detect_ec_rst_with_pre_cond | 1 | 1 | 100.00 | |||
| sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 4.710s | 2504.449us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_hw_reset | 8.880s | 6011.628us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_rw | 4.280s | 2049.464us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_bit_bash | 22.650s | 36408.751us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_aliasing | 2.710s | 2478.099us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| sysrst_ctrl_csr_mem_rw_with_rand_reset | 2.070s | 2220.787us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| sysrst_ctrl_csr_rw | 4.280s | 2049.464us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_aliasing | 2.710s | 2478.099us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| combo_detect | 1 | 1 | 100.00 | |||
| sysrst_ctrl_combo_detect | 66.710s | 161460.214us | 1 | 1 | 100.00 | |
| combo_detect_with_pre_cond | 0 | 1 | 0.00 | |||
| sysrst_ctrl_combo_detect_with_pre_cond | 32.030s | 19520.915us | 0 | 1 | 0.00 | |
| auto_block_key_outputs | 1 | 1 | 100.00 | |||
| sysrst_ctrl_auto_blk_key_output | 280.130s | 150686.172us | 1 | 1 | 100.00 | |
| keyboard_input_triggered_interrupt | 1 | 1 | 100.00 | |||
| sysrst_ctrl_edge_detect | 5.960s | 4054.961us | 1 | 1 | 100.00 | |
| pin_output_keyboard_inversion_control | 1 | 1 | 100.00 | |||
| sysrst_ctrl_pin_override_test | 2.120s | 2526.350us | 1 | 1 | 100.00 | |
| pin_input_value_accessibility | 1 | 1 | 100.00 | |||
| sysrst_ctrl_pin_access_test | 2.360s | 2087.746us | 1 | 1 | 100.00 | |
| ec_power_on_reset | 1 | 1 | 100.00 | |||
| sysrst_ctrl_ec_pwr_on_rst | 4.740s | 2469.219us | 1 | 1 | 100.00 | |
| flash_write_protect_output | 1 | 1 | 100.00 | |||
| sysrst_ctrl_flash_wr_prot_out | 6.750s | 2609.275us | 1 | 1 | 100.00 | |
| ultra_low_power_test | 1 | 1 | 100.00 | |||
| sysrst_ctrl_ultra_low_pwr | 1.930s | 6371.655us | 1 | 1 | 100.00 | |
| sysrst_ctrl_feature_disable | 1 | 1 | 100.00 | |||
| sysrst_ctrl_feature_disable | 16.920s | 35687.013us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| sysrst_ctrl_stress_all | 8.120s | 13686.672us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| sysrst_ctrl_alert_test | 4.350s | 2015.141us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| sysrst_ctrl_intr_test | 4.740s | 2019.255us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| sysrst_ctrl_tl_errors | 2.580s | 2553.878us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| sysrst_ctrl_tl_errors | 2.580s | 2553.878us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| sysrst_ctrl_csr_hw_reset | 8.880s | 6011.628us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_rw | 4.280s | 2049.464us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_aliasing | 2.710s | 2478.099us | 1 | 1 | 100.00 | |
| sysrst_ctrl_same_csr_outstanding | 15.780s | 8038.420us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| sysrst_ctrl_csr_hw_reset | 8.880s | 6011.628us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_rw | 4.280s | 2049.464us | 1 | 1 | 100.00 | |
| sysrst_ctrl_csr_aliasing | 2.710s | 2478.099us | 1 | 1 | 100.00 | |
| sysrst_ctrl_same_csr_outstanding | 15.780s | 8038.420us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| sysrst_ctrl_sec_cm | 42.160s | 22013.080us | 1 | 1 | 100.00 | |
| sysrst_ctrl_tl_intg_err | 44.630s | 42544.549us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| sysrst_ctrl_tl_intg_err | 44.630s | 42544.549us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| sysrst_ctrl_stress_all_with_rand_reset | 9.540s | 5102.671us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) | 1 test run | |||
| sysrst_ctrl_combo_detect_with_pre_cond | 74339015190963136230943754835241967780249529285172729389138578481192536158803 | 671 |
UVM_ERROR @ 19520914891 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 19520914891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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