Simulation Results: uart

 
20/08/2026 15:30:29 DVSim: v1.51.0 sha: 83fc48e json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 79.34 %
  • code
  • 91.80 %
  • assert
  • 98.85 %
  • func
  • 47.37 %
  • line
  • 99.17 %
  • branch
  • 96.74 %
  • cond
  • 96.62 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.350s 672.082us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.940s 1070.751us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.630s 17.254us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.950s 151.737us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.800s 114.177us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.790s 13.431us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.630s 17.254us 1 1 100.00
uart_csr_aliasing 0.800s 114.177us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 3.600s 3032.449us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.350s 672.082us 1 1 100.00
uart_tx_rx 3.600s 3032.449us 1 1 100.00
parity_error 2 2 100.00
uart_intr 110.100s 270532.185us 1 1 100.00
uart_rx_parity_err 5.270s 10434.426us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 3.600s 3032.449us 1 1 100.00
uart_intr 110.100s 270532.185us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 23.870s 109889.100us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 15.880s 21690.399us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 32.240s 130167.323us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 110.100s 270532.185us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 110.100s 270532.185us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 110.100s 270532.185us 1 1 100.00
perf 1 1 100.00
uart_perf 36.470s 5532.221us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 0.760s 128.121us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 0.760s 128.121us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 4.410s 19429.729us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 5.920s 5047.505us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.920s 1856.912us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 27.130s 6296.613us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 154.040s 117110.947us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 1.700s 1528.666us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.810s 29.365us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.690s 39.270us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.120s 244.563us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.120s 244.563us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.940s 1070.751us 1 1 100.00
uart_csr_rw 0.630s 17.254us 1 1 100.00
uart_csr_aliasing 0.800s 114.177us 1 1 100.00
uart_same_csr_outstanding 0.760s 12.394us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.940s 1070.751us 1 1 100.00
uart_csr_rw 0.630s 17.254us 1 1 100.00
uart_csr_aliasing 0.800s 114.177us 1 1 100.00
uart_same_csr_outstanding 0.760s 12.394us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.100s 157.344us 1 1 100.00
uart_tl_intg_err 0.880s 325.799us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.880s 325.799us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 11.780s 3721.166us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:374) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_stress_all 101631592198174933120821966327247432289859739172035908697511971827833052115764 81
UVM_ERROR @ 261989001 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 261989001 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 349489701 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 408781842 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0