Simulation Results: adc_ctrl

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 70.86 %
  • code
  • 97.87 %
  • assert
  • 96.76 %
  • func
  • 17.96 %
  • line
  • 99.02 %
  • branch
  • 98.45 %
  • cond
  • 94.58 %
  • toggle
  • 100.00 %
  • FSM
  • 97.30 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 11.690s 5756.583us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 4.520s 1206.931us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.990s 505.650us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 19.080s 9384.061us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 3.040s 747.250us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.160s 450.193us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.990s 505.650us 1 1 100.00
adc_ctrl_csr_aliasing 3.040s 747.250us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 79.290s 39292.335us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 25.270s 35867.202us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 20.150s 37606.209us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 54.780s 37474.327us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 66.620s 71334.244us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 51.620s 70402.286us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 144.590s 66976.508us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 36.050s 19060.232us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 4.040s 2969.905us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 44.820s 22400.183us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 221.330s 105292.726us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 51.340s 105016.755us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.960s 346.077us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 2.540s 532.238us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.490s 394.793us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.490s 394.793us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 4.520s 1206.931us 1 1 100.00
adc_ctrl_csr_rw 0.990s 505.650us 1 1 100.00
adc_ctrl_csr_aliasing 3.040s 747.250us 1 1 100.00
adc_ctrl_same_csr_outstanding 5.000s 4753.840us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 4.520s 1206.931us 1 1 100.00
adc_ctrl_csr_rw 0.990s 505.650us 1 1 100.00
adc_ctrl_csr_aliasing 3.040s 747.250us 1 1 100.00
adc_ctrl_same_csr_outstanding 5.000s 4753.840us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 3.700s 8317.315us 1 1 100.00
adc_ctrl_tl_intg_err 18.620s 8188.412us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 18.620s 8188.412us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 5.030s 1619.133us 1 1 100.00