Simulation Results: aes/masked

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.40 %
  • code
  • 93.60 %
  • assert
  • 98.23 %
  • func
  • 70.36 %
  • block
  • 94.26 %
  • line
  • 95.94 %
  • branch
  • 87.16 %
  • toggle
  • 97.99 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 5.000s 200.319us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 68.628us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 108.460us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 3.000s 100.942us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 7.000s 255.159us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 174.410us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 115.438us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 3.000s 100.942us 1 1 100.00
aes_csr_aliasing 3.000s 174.410us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 68.628us 1 1 100.00
aes_config_error 4.000s 410.887us 1 1 100.00
aes_stress 3.000s 96.924us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 68.628us 1 1 100.00
aes_config_error 4.000s 410.887us 1 1 100.00
aes_stress 3.000s 96.924us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 96.924us 1 1 100.00
aes_b2b 3.000s 60.879us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 96.924us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 68.628us 1 1 100.00
aes_config_error 4.000s 410.887us 1 1 100.00
aes_stress 3.000s 96.924us 1 1 100.00
aes_alert_reset 6.000s 211.988us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 4.000s 196.442us 1 1 100.00
aes_config_error 4.000s 410.887us 1 1 100.00
aes_alert_reset 6.000s 211.988us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 322.014us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 14.000s 1284.767us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 6.000s 211.988us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 96.924us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 96.924us 1 1 100.00
aes_sideload 3.000s 88.490us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 127.125us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 3.000s 209.131us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 76.489us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 73.836us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 73.836us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 108.460us 1 1 100.00
aes_csr_rw 3.000s 100.942us 1 1 100.00
aes_csr_aliasing 3.000s 174.410us 1 1 100.00
aes_same_csr_outstanding 2.000s 67.733us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 108.460us 1 1 100.00
aes_csr_rw 3.000s 100.942us 1 1 100.00
aes_csr_aliasing 3.000s 174.410us 1 1 100.00
aes_same_csr_outstanding 2.000s 67.733us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 4.000s 45.490us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 4.000s 113.800us 0 1 0.00
aes_control_fi 2.000s 51.165us 1 1 100.00
aes_cipher_fi 2.000s 55.659us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 79.336us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 79.336us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 79.336us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 79.336us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 161.246us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 1622.742us 1 1 100.00
aes_tl_intg_err 3.000s 317.853us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 317.853us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 6.000s 211.988us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 79.336us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 79.336us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 68.628us 1 1 100.00
aes_stress 3.000s 96.924us 1 1 100.00
aes_alert_reset 6.000s 211.988us 1 1 100.00
aes_core_fi 3.000s 157.295us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 4.000s 410.887us 1 1 100.00
aes_stress 3.000s 96.924us 1 1 100.00
aes_core_fi 3.000s 157.295us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 79.336us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 67.312us 1 1 100.00
aes_stress 3.000s 96.924us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 96.924us 1 1 100.00
aes_sideload 3.000s 88.490us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 67.312us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 67.312us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 67.312us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 67.312us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 67.312us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 96.924us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 96.924us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 4.000s 113.800us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 4.000s 113.800us 0 1 0.00
aes_control_fi 2.000s 51.165us 1 1 100.00
aes_cipher_fi 2.000s 55.659us 1 1 100.00
aes_ctr_fi 2.000s 117.527us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 4.000s 113.800us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 4.000s 113.800us 0 1 0.00
aes_control_fi 2.000s 51.165us 1 1 100.00
aes_cipher_fi 2.000s 55.659us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 55.659us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 4.000s 113.800us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 4.000s 113.800us 0 1 0.00
aes_control_fi 2.000s 51.165us 1 1 100.00
aes_ctr_fi 2.000s 117.527us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 4.000s 113.800us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 4.000s 113.800us 0 1 0.00
aes_control_fi 2.000s 51.165us 1 1 100.00
aes_cipher_fi 2.000s 55.659us 1 1 100.00
aes_ctr_fi 2.000s 117.527us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 6.000s 211.988us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 4.000s 113.800us 0 1 0.00
aes_control_fi 2.000s 51.165us 1 1 100.00
aes_cipher_fi 2.000s 55.659us 1 1 100.00
aes_ctr_fi 2.000s 117.527us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 4.000s 113.800us 0 1 0.00
aes_control_fi 2.000s 51.165us 1 1 100.00
aes_cipher_fi 2.000s 55.659us 1 1 100.00
aes_ctr_fi 2.000s 117.527us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 4.000s 113.800us 0 1 0.00
aes_control_fi 2.000s 51.165us 1 1 100.00
aes_ctr_fi 2.000s 117.527us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 4.000s 113.800us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 4.000s 113.800us 0 1 0.00
aes_control_fi 2.000s 51.165us 1 1 100.00
aes_cipher_fi 2.000s 55.659us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 13.000s 1211.851us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_reseed 105259173724197580154302997236603229136843371292298938013800994489769833508214 10642
UVM_INFO @ 45489732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 10698265002341410334629337688150934511868099731840296981442941026940497431319 346
UVM_INFO @ 1211851135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 92639062600511557786821442684736123540551345859464057134693044361793524960809 17626
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0