Simulation Results: aes/unmasked

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.32 %
  • code
  • 89.67 %
  • assert
  • 97.73 %
  • func
  • 74.57 %
  • block
  • 89.36 %
  • line
  • 91.54 %
  • branch
  • 80.25 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
94.12%
V2S
81.25%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 68.394us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 64.809us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 55.651us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 96.347us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 861.830us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 321.832us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 80.973us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 96.347us 1 1 100.00
aes_csr_aliasing 3.000s 321.832us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 64.809us 1 1 100.00
aes_config_error 3.000s 79.573us 1 1 100.00
aes_stress 4.000s 382.150us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 64.809us 1 1 100.00
aes_config_error 3.000s 79.573us 1 1 100.00
aes_stress 4.000s 382.150us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 382.150us 1 1 100.00
aes_b2b 7.000s 142.686us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 382.150us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 64.809us 1 1 100.00
aes_config_error 3.000s 79.573us 1 1 100.00
aes_stress 4.000s 382.150us 1 1 100.00
aes_alert_reset 4.000s 567.599us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 148.479us 1 1 100.00
aes_config_error 3.000s 79.573us 1 1 100.00
aes_alert_reset 4.000s 567.599us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 5.000s 215.092us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 1173.028us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 567.599us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 382.150us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 382.150us 1 1 100.00
aes_sideload 4.000s 430.663us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 179.195us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 12.000s 720.759us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 217.300us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 4.000s 488.077us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 4.000s 488.077us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 55.651us 1 1 100.00
aes_csr_rw 2.000s 96.347us 1 1 100.00
aes_csr_aliasing 3.000s 321.832us 1 1 100.00
aes_same_csr_outstanding 2.000s 112.512us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 55.651us 1 1 100.00
aes_csr_rw 2.000s 96.347us 1 1 100.00
aes_csr_aliasing 3.000s 321.832us 1 1 100.00
aes_same_csr_outstanding 2.000s 112.512us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 2.000s 6.444us 0 1 0.00
fault_inject 1 3 33.33
aes_fi 3.000s 80.311us 0 1 0.00
aes_control_fi 1.000s 51.607us 1 1 100.00
aes_cipher_fi 61.000s 0.000us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 120.014us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 120.014us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 120.014us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 120.014us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 143.475us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 1280.566us 1 1 100.00
aes_tl_intg_err 4.000s 619.751us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 4.000s 619.751us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 567.599us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 120.014us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 120.014us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 64.809us 1 1 100.00
aes_stress 4.000s 382.150us 1 1 100.00
aes_alert_reset 4.000s 567.599us 1 1 100.00
aes_core_fi 2.000s 102.143us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 79.573us 1 1 100.00
aes_stress 4.000s 382.150us 1 1 100.00
aes_core_fi 2.000s 102.143us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 120.014us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 197.742us 1 1 100.00
aes_stress 4.000s 382.150us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 382.150us 1 1 100.00
aes_sideload 4.000s 430.663us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 197.742us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 197.742us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 197.742us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 197.742us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 197.742us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 382.150us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 382.150us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 80.311us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 3.000s 80.311us 0 1 0.00
aes_control_fi 1.000s 51.607us 1 1 100.00
aes_cipher_fi 61.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 87.043us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 80.311us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 3.000s 80.311us 0 1 0.00
aes_control_fi 1.000s 51.607us 1 1 100.00
aes_cipher_fi 61.000s 0.000us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 61.000s 0.000us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 80.311us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 80.311us 0 1 0.00
aes_control_fi 1.000s 51.607us 1 1 100.00
aes_ctr_fi 2.000s 87.043us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 80.311us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 3.000s 80.311us 0 1 0.00
aes_control_fi 1.000s 51.607us 1 1 100.00
aes_cipher_fi 61.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 87.043us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 567.599us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 3.000s 80.311us 0 1 0.00
aes_control_fi 1.000s 51.607us 1 1 100.00
aes_cipher_fi 61.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 87.043us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 3.000s 80.311us 0 1 0.00
aes_control_fi 1.000s 51.607us 1 1 100.00
aes_cipher_fi 61.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 87.043us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 80.311us 0 1 0.00
aes_control_fi 1.000s 51.607us 1 1 100.00
aes_ctr_fi 2.000s 87.043us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 80.311us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 3.000s 80.311us 0 1 0.00
aes_control_fi 1.000s 51.607us 1 1 100.00
aes_cipher_fi 61.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 8.251us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_reseed 102562395784506649979424697434978067342732911183110793765536090748054556671844 548
UVM_INFO @ 6444492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 54748894161897132721668342356338665166312014212616008765199932028595621436601 27029
UVM_INFO @ 720759489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 9402265781499814683568684799081474402503694734684207025446812669843112282830 8478
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 4
----| Expected corrupted: 0
Job timed out after * minutes 1 test run
aes_cipher_fi 44878755344780704623597524022026061909479530998423016446642798883115799651752 None
UVM_FATAL (aes_base_vseq.sv:87) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 114090515882277030840719529897363743348163262222212504262728686647533359119123 109
UVM_INFO @ 8251286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---