Simulation Results: alert_handler

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 89.87 %
  • code
  • 90.90 %
  • assert
  • 98.06 %
  • func
  • 80.66 %
  • line
  • 99.68 %
  • branch
  • 98.25 %
  • cond
  • 90.56 %
  • toggle
  • 91.80 %
  • FSM
  • 74.19 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 48.220s 6097.698us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 4.500s 65.831us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.700s 137.321us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 264.480s 5386.948us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 159.160s 14529.044us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 3.210s 114.061us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.700s 137.321us 1 1 100.00
alert_handler_csr_aliasing 159.160s 14529.044us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 211.700s 14950.266us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 38.080s 2358.891us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 2471.480s 116084.385us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 8.320s 172.840us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 48.220s 6097.698us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 37.280s 3162.825us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 31.960s 549.411us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 148.780s 3881.214us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 988.940s 66945.296us 1 1 100.00
alert_handler_lpg_stub_clk 900.370s 28542.120us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 2569.900s 549995.745us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 9.680s 1067.554us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.240s 19.229us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 2.110s 9.424us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 11.230s 1380.440us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 11.230s 1380.440us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 4.500s 65.831us 1 1 100.00
alert_handler_csr_rw 3.700s 137.321us 1 1 100.00
alert_handler_csr_aliasing 159.160s 14529.044us 1 1 100.00
alert_handler_same_csr_outstanding 24.620s 1152.192us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 4.500s 65.831us 1 1 100.00
alert_handler_csr_rw 3.700s 137.321us 1 1 100.00
alert_handler_csr_aliasing 159.160s 14529.044us 1 1 100.00
alert_handler_same_csr_outstanding 24.620s 1152.192us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 82.300s 3347.209us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 82.300s 3347.209us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 82.300s 3347.209us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 82.300s 3347.209us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 404.920s 5041.382us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 22.330s 1546.106us 1 1 100.00
alert_handler_tl_intg_err 6.290s 118.785us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 6.290s 118.785us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 82.300s 3347.209us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 48.220s 6097.698us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 48.220s 6097.698us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 48.220s 6097.698us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 48.220s 6097.698us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 8.320s 172.840us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 988.940s 66945.296us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 8.320s 172.840us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2471.480s 116084.385us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2471.480s 116084.385us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 22.330s 1546.106us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 22.330s 1546.106us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 22.330s 1546.106us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 22.330s 1546.106us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 22.330s 1546.106us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 22.330s 1546.106us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 22.330s 1546.106us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 22.330s 1546.106us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 22.330s 1546.106us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 129.300s 2073.436us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 92795934253684457826599474257184579809809265440526404013311072714771570558265 164
UVM_INFO @ 1067553563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 115042843887691794129804117790167642905010314658736747247585880482131443629890 141
UVM_INFO @ 2073436049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---