Simulation Results: chip

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 71.23 %
  • code
  • 75.80 %
  • assert
  • 96.74 %
  • func
  • 41.16 %
  • line
  • 93.69 %
  • branch
  • 93.28 %
  • cond
  • 88.48 %
  • toggle
  • 70.20 %
  • FSM
  • 33.33 %
Validation stages
V1
100.00%
V2
85.55%
V2S
50.00%
V3
58.33%
unmapped
12.50%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 3 3 100.00
chip_sw_example_rom 108.470s 2479.442us 1 1 100.00
chip_sw_example_manufacturer 281.680s 3228.851us 1 1 100.00
chip_sw_example_concurrency 198.670s 2704.249us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 339.890s 7167.349us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 692.530s 12932.571us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 575.130s 10954.420us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3797.420s 30078.537us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
chip_csr_mem_rw_with_rand_reset 819.710s 12630.550us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3797.420s 30078.537us 1 1 100.00
chip_csr_rw 692.530s 12932.571us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 6.730s 44.819us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 358.970s 3429.822us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 358.970s 3429.822us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 358.970s 3429.822us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 436.330s 4112.544us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 436.330s 4112.544us 1 1 100.00
chip_sw_uart_tx_rx_idx1 487.260s 4141.524us 1 1 100.00
chip_sw_uart_tx_rx_idx2 421.830s 3622.729us 1 1 100.00
chip_sw_uart_tx_rx_idx3 440.420s 4570.333us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 442.560s 3362.194us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2152.190s 13163.040us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 330.270s 4169.745us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 482.840s 8818.049us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 482.840s 8818.049us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 204.720s 3214.610us 1 1 100.00
chip_sw_sleep_pin_wake 0 1 0.00
chip_sw_sleep_pin_wake 208.310s 2652.408us 0 1 0.00
chip_sw_sleep_pin_retention 0 1 0.00
chip_sw_sleep_pin_retention 207.470s 2839.426us 0 1 0.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 153.720s 2493.968us 1 1 100.00
chip_tap_straps_testunlock0 254.610s 3755.795us 1 1 100.00
chip_tap_straps_rma 405.780s 6653.865us 1 1 100.00
chip_tap_straps_prod 112.400s 2075.339us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 619.660s 6092.548us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 619.660s 6092.548us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 790.870s 7163.552us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 2269.180s 14234.269us 0 1 0.00
chip_sw_ast_sys_clk_jitter 8 8 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4423.840s 19385.269us 1 1 100.00
chip_sw_aes_enc_jitter_en 196.670s 2934.211us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 877.890s 6330.351us 1 1 100.00
chip_sw_hmac_enc_jitter_en 222.970s 2531.722us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 1954.050s 11534.617us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 301.210s 3150.681us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 480.480s 4568.231us 1 1 100.00
chip_sw_clkmgr_jitter 217.060s 2941.498us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 261.640s 2637.582us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 1 2 50.00
chip_sw_sensor_ctrl_alert 830.580s 8357.992us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 138.710s 2187.008us 0 1 0.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 217.760s 2701.793us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 0 1 0.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 138.710s 2187.008us 0 1 0.00
chip_sw_smoketest 16 16 100.00
chip_sw_aes_smoketest 258.540s 2947.029us 1 1 100.00
chip_sw_aon_timer_smoketest 237.910s 3039.598us 1 1 100.00
chip_sw_clkmgr_smoketest 182.690s 2707.637us 1 1 100.00
chip_sw_csrng_smoketest 217.210s 2852.696us 1 1 100.00
chip_sw_entropy_src_smoketest 1024.090s 6801.877us 1 1 100.00
chip_sw_gpio_smoketest 255.010s 2912.530us 1 1 100.00
chip_sw_hmac_smoketest 253.300s 3252.971us 1 1 100.00
chip_sw_kmac_smoketest 233.120s 2655.638us 1 1 100.00
chip_sw_otbn_smoketest 1770.010s 10304.768us 1 1 100.00
chip_sw_pwrmgr_smoketest 425.080s 4819.096us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 383.240s 5157.098us 1 1 100.00
chip_sw_rv_plic_smoketest 234.850s 2761.316us 1 1 100.00
chip_sw_rv_timer_smoketest 223.320s 2886.024us 1 1 100.00
chip_sw_rstmgr_smoketest 255.570s 2995.034us 1 1 100.00
chip_sw_sram_ctrl_smoketest 214.100s 2447.587us 1 1 100.00
chip_sw_uart_smoketest 252.120s 3177.716us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 201.370s 2653.382us 1 1 100.00
chip_sw_rom_functests 1 1 100.00
rom_keymgr_dpe_functest 380.510s 4251.478us 1 1 100.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 20991.820s 128164.462us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3843.450s 16016.760us 1 1 100.00
chip_sw_rom_raw_unlock 1 1 100.00
rom_raw_unlock 471.000s 7958.586us 1 1 100.00
chip_sw_power_idle_load 1 1 100.00
chip_sw_power_idle_load 481.560s 3869.695us 1 1 100.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 227.800s 3797.519us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 13200.152s 0.000us 0 1 0.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 3600.179s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 3600.179s 0.000us 0 1 0.00
tl_d_outstanding_access 3 4 75.00
chip_csr_aliasing 3797.420s 30078.537us 1 1 100.00
chip_same_csr_outstanding 1639.310s 17256.817us 0 1 0.00
chip_csr_hw_reset 339.890s 7167.349us 1 1 100.00
chip_csr_rw 692.530s 12932.571us 1 1 100.00
tl_d_partial_access 3 4 75.00
chip_csr_aliasing 3797.420s 30078.537us 1 1 100.00
chip_same_csr_outstanding 1639.310s 17256.817us 0 1 0.00
chip_csr_hw_reset 339.890s 7167.349us 1 1 100.00
chip_csr_rw 692.530s 12932.571us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 48.800s 1680.999us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 5.830s 44.126us 1 1 100.00
xbar_smoke_large_delays 62.560s 9618.298us 1 1 100.00
xbar_smoke_slow_rsp 49.540s 5252.791us 1 1 100.00
xbar_random_zero_delays 24.460s 394.809us 1 1 100.00
xbar_random_large_delays 221.130s 32673.387us 1 1 100.00
xbar_random_slow_rsp 37.190s 2536.257us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 41.020s 1083.011us 1 1 100.00
xbar_error_and_unmapped_addr 10.290s 93.428us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 4.010s 21.288us 1 1 100.00
xbar_error_and_unmapped_addr 10.290s 93.428us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 14.700s 258.292us 1 1 100.00
xbar_access_same_device_slow_rsp 236.750s 24780.271us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 27.180s 941.171us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 156.980s 5399.940us 1 1 100.00
xbar_stress_all_with_error 162.070s 3073.679us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 270.160s 3467.263us 1 1 100.00
xbar_stress_all_with_reset_error 221.210s 3826.797us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3843.450s 16016.760us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 3483.690s 35899.794us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 4209.650s 22740.858us 1 1 100.00
rom_e2e_boot_policy_valid 15 15 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2867.490s 11116.509us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 3950.980s 16579.293us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 3850.890s 15776.213us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 4050.370s 15981.524us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 3918.530s 14791.732us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 3036.390s 11156.996us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 3942.630s 15818.019us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 4035.420s 15758.404us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 4118.390s 17012.384us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 3788.070s 14838.542us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 5136.920s 17273.583us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 6751.810s 24938.158us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 7063.000s 26624.808us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 6653.620s 25511.281us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 6760.150s 24394.908us 1 1 100.00
rom_e2e_sigverify_always 15 15 100.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 5377.840s 21353.340us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 6327.310s 23084.292us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 6442.590s 22636.203us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 7002.760s 28994.090us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 6747.480s 27765.832us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 2820.340s 11221.076us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 3565.360s 14256.921us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 3572.410s 14405.342us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 3628.410s 14121.881us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 3143.530s 13386.231us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 3095.960s 19346.870us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 3825.950s 21180.178us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 3975.550s 23255.628us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 3782.290s 22551.106us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 3671.240s 20300.414us 1 1 100.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 2944.840s 10737.436us 1 1 100.00
rom_e2e_asm_init_dev 4081.730s 16040.059us 1 1 100.00
rom_e2e_asm_init_prod 3809.540s 15614.696us 1 1 100.00
rom_e2e_asm_init_prod_end 4011.570s 16183.938us 1 1 100.00
rom_e2e_asm_init_rma 3850.600s 14958.742us 1 1 100.00
rom_e2e_keymgr_dpe_init 3 3 100.00
rom_e2e_keymgr_dpe_init_rom_ext_meas 7364.700s 30341.315us 1 1 100.00
rom_e2e_keymgr_dpe_init_rom_ext_no_meas 7421.580s 30751.698us 1 1 100.00
rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas 7605.400s 29337.038us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3916.460s 16329.495us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.191s 0.000us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.191s 0.000us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 195.230s 2518.517us 1 1 100.00
chip_sw_aes_enc_jitter_en 196.670s 2934.211us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 207.480s 2749.106us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 187.720s 2216.836us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_dpe_sideload_aes 1742.720s 10320.722us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 237.370s 3048.287us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 398.930s 5370.387us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 567.130s 5447.760us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 563.070s 4597.503us 1 1 100.00
chip_plic_all_irqs_10 386.460s 3810.538us 1 1 100.00
chip_plic_all_irqs_20 485.420s 3998.692us 1 1 100.00
chip_sw_alert_handler_entropy 0 1 0.00
chip_sw_alert_handler_entropy 249.400s 3137.156us 0 1 0.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1248.230s 11614.466us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 512.100s 6535.053us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 204.520s 2805.507us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 224.840s 2505.764us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1456.290s 8687.960us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1206.150s 6736.208us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 976.530s 7522.528us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 11844.750s 255417.409us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 390.510s 4190.896us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 425.080s 4819.096us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 390.510s 4190.896us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 671.520s 8112.253us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 671.520s 8112.253us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 428.100s 6609.066us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 498.870s 4961.082us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 721.570s 5830.888us 1 1 100.00
chip_sw_aes_idle 187.720s 2216.836us 1 1 100.00
chip_sw_hmac_enc_idle 254.020s 3158.980us 1 1 100.00
chip_sw_kmac_idle 218.860s 2388.046us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 411.740s 4245.162us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 283.250s 3871.515us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 319.580s 4721.630us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 397.580s 3627.652us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 983.260s 10467.240us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 542.280s 4322.558us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 539.550s 4577.406us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 423.670s 3741.484us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 427.080s 4641.373us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 473.910s 4380.390us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 480.560s 4491.934us 1 1 100.00
chip_sw_ast_clk_outputs 790.870s 7163.552us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1662.100s 25955.840us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 423.670s 3741.484us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 427.080s 4641.373us 1 1 100.00
chip_sw_clkmgr_jitter 8 8 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4423.840s 19385.269us 1 1 100.00
chip_sw_aes_enc_jitter_en 196.670s 2934.211us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 877.890s 6330.351us 1 1 100.00
chip_sw_hmac_enc_jitter_en 222.970s 2531.722us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 1954.050s 11534.617us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 301.210s 3150.681us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 480.480s 4568.231us 1 1 100.00
chip_sw_clkmgr_jitter 217.060s 2941.498us 1 1 100.00
chip_sw_clkmgr_extended_range 8 8 100.00
chip_sw_clkmgr_jitter_reduced_freq 208.490s 2599.613us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4224.230s 25094.248us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 213.590s 3152.206us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 256.560s 2792.438us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq 1774.330s 12066.023us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 248.570s 3075.464us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 449.100s 4916.544us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 20713.210s 196644.125us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 790.870s 7163.552us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 0 1 0.00
chip_sw_clkmgr_sleep_frequency 448.150s 4050.542us 0 1 0.00
chip_sw_clkmgr_reset_frequency 0 1 0.00
chip_sw_clkmgr_reset_frequency 712.260s 11108.426us 0 1 0.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 567.130s 5447.760us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1456.290s 8687.960us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2685.090s 23965.154us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 349.800s 3684.354us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 755.010s 8746.151us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 247.820s 2519.803us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 4636.720s 21815.403us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 240.670s 3055.832us 1 1 100.00
chip_sw_edn_entropy_reqs 904.710s 6754.489us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 240.670s 3055.832us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2685.090s 23965.154us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 253.590s 2845.888us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 213.510s 2948.184us 1 1 100.00
chip_sw_hmac_enc_jitter_en 222.970s 2531.722us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 254.020s 3158.980us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1858.610s 11062.853us 1 1 100.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 2058.170s 12010.220us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 512.520s 4532.943us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 502.690s 4811.468us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 554.360s 4866.846us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 364.990s 3454.922us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 2 2 100.00
chip_sw_keymgr_dpe_key_derivation 1924.340s 12252.446us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 1954.050s 11534.617us 1 1 100.00
chip_sw_keymgr_dpe_sideload_kmac 1 1 100.00
chip_sw_keymgr_dpe_sideload_kmac 1427.050s 8856.012us 1 1 100.00
chip_sw_keymgr_dpe_sideload_aes 1 1 100.00
chip_sw_keymgr_dpe_sideload_aes 1742.720s 10320.722us 1 1 100.00
chip_sw_keymgr_dpe_sideload_otbn 0 1 0.00
chip_sw_keymgr_dpe_sideload_otbn 3600.283s 0.000us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 196.430s 3200.098us 1 1 100.00
chip_sw_kmac_mode_kmac 270.580s 2682.960us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 301.210s 3150.681us 1 1 100.00
chip_sw_kmac_app_keymgr_dpe 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 1924.340s 12252.446us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 825.130s 13156.153us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 373.000s 8530.543us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 930.890s 6450.681us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 218.860s 2388.046us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 398.930s 5370.387us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 153.720s 2493.968us 1 1 100.00
chip_tap_straps_rma 405.780s 6653.865us 1 1 100.00
chip_tap_straps_prod 112.400s 2075.339us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 249.070s 2838.820us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 825.130s 13156.153us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 825.130s 13156.153us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 825.130s 13156.153us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_dpe_key_derivation_prod 1866.530s 11201.151us 1 1 100.00
chip_sw_lc_ctrl_broadcast 18 21 85.71
chip_sw_rram_rma_unlocked 463.320s 10010.140us 0 1 0.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 314.850s 3281.136us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 670.920s 6068.188us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 767.750s 6344.244us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 621.200s 5987.433us 0 1 0.00
chip_sw_lc_ctrl_transition 825.130s 13156.153us 1 1 100.00
chip_sw_rram_ctrl_lc_rw_en 504.110s 4940.282us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 1924.340s 12252.446us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 764.110s 18074.998us 1 1 100.00
chip_sw_sram_ctrl_execution_main 567.990s 7807.780us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1662.100s 25955.840us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 542.280s 4322.558us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 539.550s 4577.406us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 423.670s 3741.484us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 427.080s 4641.373us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 473.910s 4380.390us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 480.560s 4491.934us 1 1 100.00
chip_tap_straps_dev 153.720s 2493.968us 1 1 100.00
chip_tap_straps_rma 405.780s 6653.865us 1 1 100.00
chip_tap_straps_prod 112.400s 2075.339us 1 1 100.00
chip_rv_dm_lc_disabled 50.730s 2256.913us 0 1 0.00
chip_lc_scrap 3 4 75.00
chip_sw_lc_ctrl_rma_to_scrap 439.960s 5112.459us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 446.750s 8540.333us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 630.580s 11145.965us 0 1 0.00
chip_sw_lc_ctrl_rand_to_scrap 400.820s 5890.728us 1 1 100.00
chip_lc_test_locked 0 2 0.00
chip_sw_lc_walkthrough_testunlocks 3005.170s 60000.000us 0 1 0.00
chip_rv_dm_lc_disabled 50.730s 2256.913us 0 1 0.00
chip_sw_lc_walkthrough 1 5 20.00
chip_sw_lc_walkthrough_dev 1479.180s 18501.460us 0 1 0.00
chip_sw_lc_walkthrough_prod 1749.750s 20297.151us 0 1 0.00
chip_sw_lc_walkthrough_prodend 1249.230s 16122.443us 1 1 100.00
chip_sw_lc_walkthrough_rma 886.990s 13164.943us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 3005.170s 60000.000us 0 1 0.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 187.180s 4152.268us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 197.880s 3381.654us 1 1 100.00
rom_volatile_raw_unlock 273.340s 5127.979us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 4117.730s 17507.136us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4423.840s 19385.269us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 721.570s 5830.888us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 721.570s 5830.888us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 721.570s 5830.888us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 374.310s 3314.094us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 825.130s 13156.153us 1 1 100.00
chip_sw_otp_ctrl_keys 3 4 75.00
chip_sw_otbn_mem_scramble 374.310s 3314.094us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 1924.340s 12252.446us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 510.100s 4312.070us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 3600.163s 0.000us 0 1 0.00
chip_sw_otp_ctrl_entropy 3 4 75.00
chip_sw_otbn_mem_scramble 374.310s 3314.094us 1 1 100.00
chip_sw_keymgr_dpe_key_derivation 1924.340s 12252.446us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 510.100s 4312.070us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 3600.163s 0.000us 0 1 0.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 825.130s 13156.153us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 554.980s 5590.982us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 249.070s 2838.820us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 4 5 80.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 314.850s 3281.136us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 670.920s 6068.188us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 767.750s 6344.244us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 621.200s 5987.433us 0 1 0.00
chip_sw_lc_ctrl_transition 825.130s 13156.153us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1040.720s 7251.044us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 397.540s 7743.994us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 234.460s 2659.051us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 165.370s 2396.071us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 628.130s 7420.937us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 359.140s 5050.959us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 817.610s 19531.141us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 2 2 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 981.060s 13606.646us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 671.520s 8112.253us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 245.770s 3945.069us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 467.390s 4147.544us 1 1 100.00
chip_sw_pwrmgr_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 397.540s 7743.994us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 363.670s 3854.068us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1667.370s 19642.465us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 355.860s 5929.671us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 183.740s 2805.807us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 367.550s 7333.890us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 885.210s 6785.221us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1130.240s 10407.276us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1592.680s 25098.383us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 250.420s 2809.410us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 567.130s 5447.760us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 764.110s 18074.998us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 764.110s 18074.998us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1130.240s 10407.276us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 367.550s 7333.890us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 467.390s 4147.544us 1 1 100.00
chip_sw_pwrmgr_smoketest 425.080s 4819.096us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 432.060s 5059.872us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 595.750s 6602.199us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 463.710s 4506.367us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1248.230s 11614.466us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 223.350s 2940.496us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 567.130s 5447.760us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1206.150s 6736.208us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 590.320s 4645.907us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 616.690s 4458.623us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 204.230s 2879.524us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 0 1 0.00
chip_sw_rv_core_ibex_icache_invalidate 3600.163s 0.000us 0 1 0.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 595.750s 6602.199us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 595.750s 6602.199us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 211.630s 2839.659us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 925.060s 14438.645us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 1483.480s 23356.544us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 432.060s 5059.872us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 310.200s 3431.208us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 172.770s 2206.165us 0 1 0.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 405.780s 6653.865us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 50.730s 2256.913us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 563.070s 4597.503us 1 1 100.00
chip_plic_all_irqs_10 386.460s 3810.538us 1 1 100.00
chip_plic_all_irqs_20 485.420s 3998.692us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 170.010s 2524.212us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 239.470s 3064.257us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3843.450s 16016.760us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 370.890s 4528.226us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 304.190s 3256.737us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 264.770s 3126.540us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 233.750s 2546.483us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 510.100s 4312.070us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 480.480s 4568.231us 1 1 100.00
chip_sw_sleep_sram_ret_contents 0 2 0.00
chip_sw_sleep_sram_ret_contents_no_scramble 180.050s 2791.704us 0 1 0.00
chip_sw_sleep_sram_ret_contents_scramble 263.680s 3393.829us 0 1 0.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 567.990s 7807.780us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 567.130s 5447.760us 1 1 100.00
chip_sw_data_integrity_escalation 619.660s 6092.548us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 885.210s 6785.221us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1084.330s 22309.708us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 260.830s 2530.349us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 312.770s 3680.787us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 408.390s 4119.029us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1084.330s 22309.708us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1084.330s 22309.708us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 3028.360s 20753.967us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 3028.360s 20753.967us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 365.820s 5773.891us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.191s 0.000us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 216.080s 3174.571us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 187.640s 2883.912us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 358.570s 3168.678us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 422.010s 3910.717us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1039.470s 8077.967us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 6521.910s 31345.783us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 2256.060s 12345.930us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 193.740s 2531.954us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 321.170s 2807.177us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 135.420s 2329.381us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 12901.750s 72472.272us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1465.830s 6594.352us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 111.130s 2292.603us 0 1 0.00
rom_e2e_jtag_debug_dev 81.240s 1493.703us 0 1 0.00
rom_e2e_jtag_debug_rma 133.960s 2387.317us 0 1 0.00
rom_e2e_jtag_inject 1 3 33.33
rom_e2e_jtag_inject_test_unlocked0 316.150s 5285.689us 1 1 100.00
rom_e2e_jtag_inject_dev 77.270s 1751.561us 0 1 0.00
rom_e2e_jtag_inject_rma 104.850s 1764.131us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 76.944s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 331.430s 2891.562us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 387.790s 2688.598us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 1383.040s 6567.242us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1599.870s 9329.862us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 333.950s 2660.838us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 232.100s 2234.799us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 0 1 0.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 304.900s 4676.388us 0 1 0.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 461.170s 4682.780us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1130.240s 10407.276us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 111.130s 2292.603us 0 1 0.00
rom_e2e_jtag_debug_dev 81.240s 1493.703us 0 1 0.00
rom_e2e_jtag_debug_rma 133.960s 2387.317us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 483.700s 4425.451us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 567.130s 5447.760us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 6591.120s 37538.678us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 6591.120s 37538.678us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 0 1 0.00
chip_sw_spi_device_pinmux_sleep_retention 181.820s 2817.782us 0 1 0.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 436.330s 4112.544us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3423.380s 18777.755us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 8 12.50
chip_sw_rstmgr_rst_cnsty_escalation 51.990s 10.400us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 128.550s 1929.225us 0 1 0.00
chip_sw_otp_ctrl_descrambling 258.230s 2785.378us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 229.510s 3161.409us 0 1 0.00
chip_sw_pwrmgr_sleep_wake_5_bug 9.409s 0.000us 0 1 0.00
ate_bootstrap_flash_erase 691.090s 10010.200us 0 1 0.00
ate_bootstrap_one_frame 10800.145s 0.000us 0 1 0.00
ate_bootstrap_disjoint 10800.159s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:254) scoreboard [scoreboard] alert fatal has unexpected signal int error 16 test runs
chip_sw_sleep_pin_wake 1395841388336311364448829315716220695411205324707520556792930469587950809213 381
UVM_INFO @ 2652.407558 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_retention 45971320514509251421738949717863376446933833425405878619583357786566096534980 378
UVM_INFO @ 2839.426284 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pinmux_sleep_retention 92397827847298052624518764898143629859828726258575430247205482484523829152939 373
UVM_INFO @ 2817.782500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 28556667150707569978276492925751676951292369393064596734822519435181535895328 391
UVM_INFO @ 7333.889548 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 53756296385930353773907124744434795444710018054046378432887881719246217283915 376
UVM_INFO @ 3945.068778 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_por_reset 44571073470467027993599699509538576089973164309114102615983782156983296861552 387
UVM_INFO @ 5050.958786 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 3228480030938332883104651345460351888499331845258727467186328734592035354144 467
UVM_INFO @ 19642.465432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_no_scramble 82430247381355818108577250370750340902380568996917389082899562944724731935383 376
UVM_INFO @ 2791.704336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_scramble 58002230596202786829271531057316375656231620192864979795770447873332513728863 380
UVM_INFO @ 3393.828772 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 31062490700881359744992867398996916502603370955619665157967083725489870756954 371
UVM_INFO @ 2187.007632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_sleep_frequency 34720215783472041043062368576784059526142250288607654124357730325929962870312 406
UVM_INFO @ 4050.541928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_wake_ups 109672327906180537405647372984483952593582132754003280962298956199641833687845 373
UVM_INFO @ 2396.070536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_lowpower_cancel 33065917348170510137240063431765093625787575836657715219747453532071752200034 371
UVM_INFO @ 3161.409300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_wake_ups 51066312771534412315955374276614882510888339271479087099348894549316277701648 372
UVM_INFO @ 2659.051368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_dm_access_after_wakeup 72315587276191282493441274060080168277626827759209745759438168830744674055211 383
UVM_INFO @ 2206.164592 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 41677003310330848888146827509553724557388367571365020769928491418190573034338 386
UVM_INFO @ 3797.518676 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 7 test runs
chip_sw_exit_test_unlocked_bootstrap 56480367935716753065510773377265594502655872498576185315178215971867275535495 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 109721575468025650836471020695045592700316422596927492521418481114635220361769 None
chip_sw_keymgr_dpe_sideload_otbn 89371479383536399309575221369756580958785255415250750590234053831010156926 None
chip_tl_errors 54466491331754109746905103952032168304293353819500053330877228294002980100773 None
chip_sw_rv_core_ibex_icache_invalidate 70649479698151797722278030324332713029331979795788220462647705798800016692626 None
ate_bootstrap_one_frame 24310898116077828852876261909786503803386893239351266347239648006049964382277 None
ate_bootstrap_disjoint 79402810544265553830499551913105803236662497242525936211899589797588933242188 None
Error-[NOA] Null object access 4 test runs
chip_sw_otp_ctrl_rot_auth_config 8355005935920462176442023692122063404204234497266989549627872250551138365948 374
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 36745205939418791664772987780609723893948402405982477790845519173995293699616 396
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 74018512047045922525345570677450719230710853616904056491995272213272789455734 372
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 91381293249312694137002635231163647705696625293540469220778647237881284088389 372
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 97948680479876969917563469097614400421002833673353897506512762581341190465331 432
UVM_INFO @ 18501.460080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 107995945934994748464676030941848782596522116794610879563213663852657756914701 432
UVM_INFO @ 20297.151172 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 9542749656712712954102929773928743388042507568873184995252898792892995402400 404
UVM_INFO @ 13164.942899 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:604) [debugger] Check failed pc == exp_addr (* [*] vs * [*]) 3 test runs
rom_e2e_jtag_debug_test_unlocked0 55032580204819937703292469972760721865022790496034068785999489391864098862069 352
UVM_INFO @ 2292.603000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_jtag_debug_dev 97651340049874899560145201806889993435862791480547444224288581752995995144954 352
UVM_INFO @ 1493.703000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_jtag_debug_rma 86850403051533859061997116817013183671896942739853648371330308180666885154409 352
UVM_INFO @ 2387.317000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error 2 test runs
chip_sw_alert_handler_lpg_sleep_mode_pings 82884915757157576840386097990026666242600532042565888614417977742147394152860 372
UVM_INFO @ 2505.763538 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_entropy 39633109779681791469277098480870380933967817431373505492864589038117967160781 442
UVM_INFO @ 3137.155608 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 2 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 47352998605549689873000105137915724634162100740570382006464092134314782192491 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 71822709640778758191065493646126188358343459577935330730280806089944750827493 None
Another command (pid=400162) is running. Waiting for it to complete on the server (server_pid=203519)...
Another command (pid=447025) is running. Waiting for it to complete on the server (server_pid=203519)...
Another command (pid=399030) is running. Waiting for it to complete on the server (server_pid=203519)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_ERROR @ * us: (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal triggered unexpectedly 1 test run
chip_same_csr_outstanding 48163247561969880079989028418757397172411765362153215723102632102461530346086 282
UVM_INFO @ 17256.816550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 78657102022749080598475820785500876774195480604035293770165095950987466166585 364
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch 1 test run
chip_sw_spi_device_pass_through_collision 51471747335405681972454739389298172995370667043341286557029899232675477509889 392
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_FATAL @ * us: (chip_sw_rram_rma_unlocked_vseq.sv:162) [chip_sw_rram_rma_unlocked_vseq] wait timeout occurred! 1 test run
chip_sw_rram_rma_unlocked 87924537687251220436071620653048732138899663288973010550294929698776918505549 336
UVM_INFO @ 10010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 68298744283733159825740093566051370641675383777031385855738296566856135776188 403
UVM_INFO @ 5987.433117 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 1 test run
chip_sw_otp_ctrl_escalation 45934883620153768684364557049671327810936016235130291133220288047997689109263 379
UVM_ERROR @ 2234.799408 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2234.799408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl 1 test run
chip_sw_lc_ctrl_test_locked0_to_scrap 23310899743345115344507129599581702564638381363947901009100931803041542711746 374
UVM_INFO @ 11145.964706 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue 1 test run
chip_sw_lc_walkthrough_testunlocks 19477623350547937642553002666543279913383879178473894872916225055961798223318 491
UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 1 test run
chip_sw_pwrmgr_sleep_power_glitch_reset 16039636024298627810091734442285991888917958100922848324416479609446330492339 376
UVM_ERROR @ 2805.806980 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2805.806980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:340)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 13411604636662817048318226013146711335768565655373058004268746285964825738818 370
UVM_INFO @ 3048.287219 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 53580283627766176875184779573376355552304290625768774125425644884493725309739 372
UVM_INFO @ 2805.506717 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_hmac_multistream 111122944999131315972075686056925772837221498580451735746055052005291807294344 421
UVM_INFO @ 12010.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state. 1 test run
chip_sw_clkmgr_reset_frequency 69502226036685901829648671220726659336973877758502786397812503089000814346474 399
UVM_INFO @ 11108.425522 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 55403003330341170021559920858664026866423082637303597201801645337671250752436 406
UVM_INFO @ 2891.562357 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: * 1 test run
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 28204889991504160429974456186227968502454941706384785407909471494143902290884 379
UVM_INFO @ 4676.388049 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_rv_dm_lc_disabled_vseq.sv:154) [chip_rv_dm_lc_disabled_vseq] Check failed rdata == exp_data (* [*] vs * [*]) RV_DM sbaddress* read back check failed, got *, expected * 1 test run
chip_rv_dm_lc_disabled 5855032594495363947564441330102090859680740600353976676438032076400318787983 288
UVM_INFO @ 2256.912603 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. 1 test run
chip_sw_rv_core_ibex_lockstep_glitch 48944790964167061547614826789936049710223447756310848921692587552226666785396 392
UVM_INFO @ 2329.380770 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 9656986493153490768952353844677327868450277810720448311213830330360078811031 390
UVM_INFO @ 14234.269345 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 90556638274418320051166715587507374513259901652461234966646870086043307679043 338
UVM_INFO @ 10010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---