Simulation Results: clkmgr

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 93.57 %
  • code
  • 98.28 %
  • assert
  • 95.48 %
  • func
  • 86.96 %
  • line
  • 99.00 %
  • branch
  • 98.64 %
  • cond
  • 94.56 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.190s 24.299us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.020s 50.679us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.230s 21.604us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 14.210s 1362.871us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.310s 60.772us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.370s 41.001us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.230s 21.604us 1 1 100.00
clkmgr_csr_aliasing 1.310s 60.772us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.450s 112.765us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.090s 22.751us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 1.250s 28.306us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.040s 37.042us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.190s 24.299us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 10.300s 2836.750us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 6.570s 622.434us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 10.300s 2836.750us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 2.020s 226.804us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 1.490s 116.847us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 4.910s 647.834us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 4.910s 647.834us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 1.020s 50.679us 1 1 100.00
clkmgr_csr_rw 1.230s 21.604us 1 1 100.00
clkmgr_csr_aliasing 1.310s 60.772us 1 1 100.00
clkmgr_same_csr_outstanding 1.460s 34.798us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 1.020s 50.679us 1 1 100.00
clkmgr_csr_rw 1.230s 21.604us 1 1 100.00
clkmgr_csr_aliasing 1.310s 60.772us 1 1 100.00
clkmgr_same_csr_outstanding 1.460s 34.798us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 1.240s 20.899us 0 1 0.00
clkmgr_tl_intg_err 3.040s 131.625us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.460s 110.507us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.460s 110.507us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.460s 110.507us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.460s 110.507us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 3.970s 254.893us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 3.040s 131.625us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 10.300s 2836.750us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 6.570s 622.434us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.460s 110.507us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.590s 171.422us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.350s 73.217us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.360s 67.214us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.950s 59.183us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.120s 20.785us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.230s 21.604us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.240s 20.899us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.230s 21.604us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.230s 21.604us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.240s 20.899us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 4.580s 613.484us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 72.990s 10977.087us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 115706432627245184632113255537710895400069155256802482101883483015472663032016 94
UVM_INFO @ 20899229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---