Simulation Results: edn/edn0

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 85.79 %
  • code
  • 82.35 %
  • assert
  • 95.66 %
  • func
  • 79.37 %
  • line
  • 97.45 %
  • branch
  • 91.35 %
  • cond
  • 87.23 %
  • toggle
  • 79.79 %
  • FSM
  • 55.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.250s 52.911us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.160s 60.781us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.240s 14.111us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.940s 332.023us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.270s 232.529us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.480s 27.641us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.240s 14.111us 1 1 100.00
edn_csr_aliasing 2.270s 232.529us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.720s 297.978us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.720s 297.978us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.720s 297.978us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 29.423us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.920s 146.822us 1 1 100.00
errs 1 1 100.00
edn_err 1.370s 36.845us 1 1 100.00
disable 2 2 100.00
edn_disable 1.240s 34.323us 1 1 100.00
edn_disable_auto_req_mode 1.370s 35.642us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 6.400s 411.058us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.170s 14.126us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.500s 23.569us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.610s 573.275us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.610s 573.275us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.160s 60.781us 1 1 100.00
edn_csr_rw 1.240s 14.111us 1 1 100.00
edn_csr_aliasing 2.270s 232.529us 1 1 100.00
edn_same_csr_outstanding 1.860s 36.834us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.160s 60.781us 1 1 100.00
edn_csr_rw 1.240s 14.111us 1 1 100.00
edn_csr_aliasing 2.270s 232.529us 1 1 100.00
edn_same_csr_outstanding 1.860s 36.834us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 10.820s 605.174us 1 1 100.00
edn_tl_intg_err 2.120s 170.282us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.360s 64.619us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.920s 146.822us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.820s 605.174us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.820s 605.174us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 10.820s 605.174us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 10.820s 605.174us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.920s 146.822us 1 1 100.00
edn_sec_cm 10.820s 605.174us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.920s 146.822us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.120s 170.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 47.270s 8670.479us 1 1 100.00