Simulation Results: edn/edn1

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 87.87 %
  • code
  • 83.25 %
  • assert
  • 98.44 %
  • func
  • 81.93 %
  • line
  • 98.18 %
  • branch
  • 93.51 %
  • cond
  • 90.15 %
  • toggle
  • 87.80 %
  • FSM
  • 46.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.200s 25.039us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.180s 53.178us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.150s 11.171us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.180s 211.241us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.390s 94.465us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.480s 22.449us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.150s 11.171us 1 1 100.00
edn_csr_aliasing 1.390s 94.465us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.620s 50.502us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.620s 50.502us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.620s 50.502us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.200s 30.939us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.510s 32.285us 1 1 100.00
errs 1 1 100.00
edn_err 1.240s 101.084us 1 1 100.00
disable 2 2 100.00
edn_disable 1.090s 13.464us 1 1 100.00
edn_disable_auto_req_mode 1.580s 36.124us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.540s 327.497us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.120s 22.963us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.150s 45.929us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.920s 39.357us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.920s 39.357us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.180s 53.178us 1 1 100.00
edn_csr_rw 1.150s 11.171us 1 1 100.00
edn_csr_aliasing 1.390s 94.465us 1 1 100.00
edn_same_csr_outstanding 1.380s 24.090us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.180s 53.178us 1 1 100.00
edn_csr_rw 1.150s 11.171us 1 1 100.00
edn_csr_aliasing 1.390s 94.465us 1 1 100.00
edn_same_csr_outstanding 1.380s 24.090us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.620s 2537.458us 1 1 100.00
edn_tl_intg_err 2.200s 236.699us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.290s 20.281us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.510s 32.285us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.620s 2537.458us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.620s 2537.458us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.620s 2537.458us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.620s 2537.458us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.510s 32.285us 1 1 100.00
edn_sec_cm 7.620s 2537.458us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.510s 32.285us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.200s 236.699us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 71.130s 5069.602us 1 1 100.00