Simulation Results: hmac

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 75.94 %
  • code
  • 86.53 %
  • assert
  • 97.60 %
  • func
  • 43.69 %
  • line
  • 99.64 %
  • branch
  • 99.35 %
  • cond
  • 96.30 %
  • toggle
  • 46.17 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 1.910s 183.771us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.140s 38.586us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.960s 19.105us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.370s 2386.039us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.100s 215.351us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.220s 29.714us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.960s 19.105us 1 1 100.00
hmac_csr_aliasing 2.100s 215.351us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 56.570s 89794.849us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 57.860s 1673.565us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 257.840s 19489.712us 1 1 100.00
hmac_test_sha384_vectors 28.570s 1347.344us 1 1 100.00
hmac_test_sha512_vectors 25.530s 310.482us 1 1 100.00
hmac_test_hmac256_vectors 9.520s 274.055us 1 1 100.00
hmac_test_hmac384_vectors 14.500s 648.654us 1 1 100.00
hmac_test_hmac512_vectors 16.880s 1833.342us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 30.310s 13446.702us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 1159.760s 27433.774us 1 1 100.00
error 1 1 100.00
hmac_error 44.990s 2632.301us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 38.890s 3832.871us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 1.910s 183.771us 1 1 100.00
hmac_long_msg 56.570s 89794.849us 1 1 100.00
hmac_back_pressure 57.860s 1673.565us 1 1 100.00
hmac_datapath_stress 1159.760s 27433.774us 1 1 100.00
hmac_burst_wr 30.310s 13446.702us 1 1 100.00
hmac_stress_all 141.170s 19230.413us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 1.910s 183.771us 1 1 100.00
hmac_long_msg 56.570s 89794.849us 1 1 100.00
hmac_back_pressure 57.860s 1673.565us 1 1 100.00
hmac_datapath_stress 1159.760s 27433.774us 1 1 100.00
hmac_wipe_secret 38.890s 3832.871us 1 1 100.00
hmac_test_sha256_vectors 257.840s 19489.712us 1 1 100.00
hmac_test_sha384_vectors 28.570s 1347.344us 1 1 100.00
hmac_test_sha512_vectors 25.530s 310.482us 1 1 100.00
hmac_test_hmac256_vectors 9.520s 274.055us 1 1 100.00
hmac_test_hmac384_vectors 14.500s 648.654us 1 1 100.00
hmac_test_hmac512_vectors 16.880s 1833.342us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 1.910s 183.771us 1 1 100.00
hmac_long_msg 56.570s 89794.849us 1 1 100.00
hmac_back_pressure 57.860s 1673.565us 1 1 100.00
hmac_datapath_stress 1159.760s 27433.774us 1 1 100.00
hmac_burst_wr 30.310s 13446.702us 1 1 100.00
hmac_error 44.990s 2632.301us 1 1 100.00
hmac_wipe_secret 38.890s 3832.871us 1 1 100.00
hmac_test_sha256_vectors 257.840s 19489.712us 1 1 100.00
hmac_test_sha384_vectors 28.570s 1347.344us 1 1 100.00
hmac_test_sha512_vectors 25.530s 310.482us 1 1 100.00
hmac_test_hmac256_vectors 9.520s 274.055us 1 1 100.00
hmac_test_hmac384_vectors 14.500s 648.654us 1 1 100.00
hmac_test_hmac512_vectors 16.880s 1833.342us 1 1 100.00
hmac_stress_all 141.170s 19230.413us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 141.170s 19230.413us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.750s 13.891us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.850s 66.566us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.670s 129.580us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.670s 129.580us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.140s 38.586us 1 1 100.00
hmac_csr_rw 0.960s 19.105us 1 1 100.00
hmac_csr_aliasing 2.100s 215.351us 1 1 100.00
hmac_same_csr_outstanding 2.480s 185.457us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.140s 38.586us 1 1 100.00
hmac_csr_rw 0.960s 19.105us 1 1 100.00
hmac_csr_aliasing 2.100s 215.351us 1 1 100.00
hmac_same_csr_outstanding 2.480s 185.457us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.230s 116.081us 1 1 100.00
hmac_tl_intg_err 1.960s 49.184us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.960s 49.184us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 1.910s 183.771us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.060s 153.233us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 84.710s 7763.478us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 8.640s 843.945us 1 1 100.00