Simulation Results

Simulation Results: i2c

24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
84.83 %

code
78.08 %

assert
97.46 %

func
78.96 %

line
96.01 %

branch
91.77 %

cond
85.12 %

toggle
74.04 %

FSM
43.45 %

Validation stages

V1		100.00%
V2		92.68%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	26.980s	10094.223us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	21.270s	1869.873us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.950s	23.328us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.020s	20.529us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	5.350s	1322.917us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.550s	236.842us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.530s	95.659us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.020s	20.529us	1	1	100.00
	i2c_csr_aliasing	1.550s	236.842us	1	1	100.00

38/41 passed

92.68 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.000s	373.403us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	50.910s	9978.007us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	12.800s	2943.312us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.930s	32.684us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	54.320s	28750.348us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	84.860s	7358.940us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.330s	828.170us	1	1	100.00
	i2c_host_fifo_fmt_empty	4.630s	980.149us	1	1	100.00
	i2c_host_fifo_reset_rx	4.180s	165.305us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	138.300s	10616.549us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	6.520s	1974.324us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	2.960s	327.419us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.780s	867.314us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	34.020s	25246.646us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.600s	5712.376us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	5.370s	634.095us	1	1	100.00
	i2c_target_intr_smoke	5.130s	2488.443us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.220s	178.777us	1	1	100.00
	i2c_target_fifo_reset_tx	1.230s	120.414us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	15.500s	10999.803us	1	1	100.00
	i2c_target_stress_rd	5.370s	634.095us	1	1	100.00
	i2c_target_intr_stress_wr	191.390s	26345.749us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	7.550s	1532.305us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	1.390s	292.465us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	5.480s	1284.737us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	2.680s	634.709us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.290s	383.573us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.310s	439.926us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	12.800s	2943.312us	1	1	100.00
	i2c_host_perf_precise	1.450s	41.784us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	6.520s	1974.324us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.240s	153.688us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	3.260s	2186.963us	1	1	100.00
	i2c_target_nack_acqfull_addr	3.530s	2142.693us	1	1	100.00
	i2c_target_nack_txstretch	1.740s	286.499us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	18.550s	721.873us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	2.460s	375.578us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.020s	16.598us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.980s	70.418us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.010s	265.646us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.010s	265.646us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.950s	23.328us	1	1	100.00
	i2c_csr_rw	1.020s	20.529us	1	1	100.00
	i2c_csr_aliasing	1.550s	236.842us	1	1	100.00
	i2c_same_csr_outstanding	1.620s	62.221us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.950s	23.328us	1	1	100.00
	i2c_csr_rw	1.020s	20.529us	1	1	100.00
	i2c_csr_aliasing	1.550s	236.842us	1	1	100.00
	i2c_same_csr_outstanding	1.620s	62.221us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.970s	263.148us	1	1	100.00
	i2c_sec_cm	1.030s	92.602us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.970s	263.148us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	12.930s	2158.943us	1
target_error_intr				1
	i2c_target_unexp_stop	2.190s	1018.035us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	16.900s	4974.720us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	17047852214478710613272986095199439607571601384800735078744309859999329080100	94	UVM_INFO @ 373402759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	5861193204768392317845218536587670793236614607196466681702105899484123813225	129	UVM_INFO @ 9978006991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	13169191111202243329168226874629887262587263086933298347967102455214183091974	90	UVM_INFO @ 867314441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'				1 test run
	i2c_target_unexp_stop	2320847930914413204318166625680418953214858158325387210431593458174992610765	85	UVM_ERROR @ 1018034757 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A UVM_INFO @ 1018034757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	26042120787496121622929693557878089211192027418651962962551112665910093666262	109	UVM_INFO @ 2158943086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1209) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.				1 test run
	i2c_target_stress_all_with_rand_reset	111262311875247302658459124567535568830343167321695674571272003589841825100595	97	UVM_INFO @ 4974720232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---