Simulation Results: keymgr_dpe/earlgrey

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 65.08 %
  • code
  • 82.56 %
  • assert
  • 97.67 %
  • func
  • 15.02 %
  • line
  • 97.48 %
  • branch
  • 93.77 %
  • cond
  • 86.63 %
  • toggle
  • 59.23 %
  • FSM
  • 75.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_dpe_smoke 16.350s 3178.761us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 1.240s 40.865us 1 1 100.00
csr_rw 1 1 100.00
keymgr_dpe_csr_rw 0.970s 78.253us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 5.560s 2035.512us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 3.010s 143.890us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 1.630s 99.952us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_dpe_csr_rw 0.970s 78.253us 1 1 100.00
keymgr_dpe_csr_aliasing 3.010s 143.890us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 1 1 100.00
keymgr_dpe_intr_test 0.880s 22.729us 1 1 100.00
alert_test 1 1 100.00
keymgr_dpe_alert_test 0.980s 62.881us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_dpe_tl_errors 3.110s 224.041us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_dpe_tl_errors 3.110s 224.041us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_dpe_csr_hw_reset 1.240s 40.865us 1 1 100.00
keymgr_dpe_csr_rw 0.970s 78.253us 1 1 100.00
keymgr_dpe_csr_aliasing 3.010s 143.890us 1 1 100.00
keymgr_dpe_same_csr_outstanding 2.080s 186.908us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_dpe_csr_hw_reset 1.240s 40.865us 1 1 100.00
keymgr_dpe_csr_rw 0.970s 78.253us 1 1 100.00
keymgr_dpe_csr_aliasing 3.010s 143.890us 1 1 100.00
keymgr_dpe_same_csr_outstanding 2.080s 186.908us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
keymgr_dpe_sec_cm 14.950s 2470.484us 1 1 100.00
keymgr_dpe_tl_intg_err 4.300s 182.756us 1 1 100.00
shadow_reg_update_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.960s 5.157us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.960s 5.157us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.960s 5.157us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.960s 5.157us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 2.690s 346.965us 0 1 0.00
prim_count_check 1 1 100.00
keymgr_dpe_sec_cm 14.950s 2470.484us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_dpe_sec_cm 14.950s 2470.484us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(reg2hw.control_shadowed.slot_src_sel.q < NumInstHwSlot)' 2 test runs
keymgr_dpe_shadow_reg_errors 92609442011381396557106889300659544342964451327406640522514974160239550858563 83
UVM_ERROR @ 5157488 ps: (keymgr_dpe.sv:320) [ASSERT FAILED] SrcSelInRange_A
UVM_INFO @ 5157488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_dpe_shadow_reg_errors_with_csr_rw 45110114329451436822547528483918637495488133318754994993046170423410259300891 83
UVM_ERROR @ 346965082 ps: (keymgr_dpe.sv:320) [ASSERT FAILED] SrcSelInRange_A
UVM_INFO @ 346965082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---