Simulation Results: lc_ctrl/volatile_unlock_disabled

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.65 %
  • code
  • 84.42 %
  • assert
  • 94.69 %
  • func
  • 92.83 %
  • line
  • 97.24 %
  • branch
  • 93.76 %
  • cond
  • 79.59 %
  • toggle
  • 87.98 %
  • FSM
  • 63.55 %
Validation stages
V1
83.33%
V2
96.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.180s 321.372us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.100s 19.195us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.130s 14.272us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.850s 482.294us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.390s 16.829us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
lc_ctrl_csr_mem_rw_with_rand_reset 6.430s 10050.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.130s 14.272us 1 1 100.00
lc_ctrl_csr_aliasing 1.390s 16.829us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.140s 549.244us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 10.050s 389.731us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.150s 14.873us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.170s 262.751us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.670s 299.068us 1 1 100.00
lc_errors 0 1 0.00
lc_ctrl_errors 3.160s 317.983us 0 1 0.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 8.670s 299.068us 1 1 100.00
lc_ctrl_prog_failure 3.170s 262.751us 1 1 100.00
lc_ctrl_errors 3.160s 317.983us 0 1 0.00
lc_ctrl_security_escalation 9.300s 446.740us 1 1 100.00
lc_ctrl_jtag_state_failure 32.030s 39904.903us 1 1 100.00
lc_ctrl_jtag_prog_failure 10.310s 5460.652us 1 1 100.00
lc_ctrl_jtag_errors 24.050s 15915.283us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 6.710s 389.455us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.200s 1255.351us 1 1 100.00
lc_ctrl_jtag_prog_failure 10.310s 5460.652us 1 1 100.00
lc_ctrl_jtag_errors 24.050s 15915.283us 1 1 100.00
lc_ctrl_jtag_access 2.090s 132.669us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.160s 849.106us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.920s 81.304us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.420s 167.475us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 13.370s 1197.190us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.810s 368.664us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.500s 53.896us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.510s 251.933us 1 1 100.00
lc_ctrl_jtag_alert_test 2.010s 358.861us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.600s 366.311us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.160s 39.522us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 36.810s 10112.345us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.200s 60.509us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.330s 313.499us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.330s 313.499us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.100s 19.195us 1 1 100.00
lc_ctrl_csr_rw 1.130s 14.272us 1 1 100.00
lc_ctrl_csr_aliasing 1.390s 16.829us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.210s 50.639us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.100s 19.195us 1 1 100.00
lc_ctrl_csr_rw 1.130s 14.272us 1 1 100.00
lc_ctrl_csr_aliasing 1.390s 16.829us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.210s 50.639us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.810s 253.946us 1 1 100.00
lc_ctrl_tl_intg_err 2.880s 2106.168us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.880s 2106.168us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 10.050s 389.731us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.670s 299.068us 1 1 100.00
lc_ctrl_sec_cm 6.810s 253.946us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.670s 299.068us 1 1 100.00
lc_ctrl_sec_cm 6.810s 253.946us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.670s 299.068us 1 1 100.00
lc_ctrl_sec_cm 6.810s 253.946us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.670s 299.068us 1 1 100.00
lc_ctrl_sec_cm 6.810s 253.946us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.670s 299.068us 1 1 100.00
lc_ctrl_sec_cm 6.810s 253.946us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.670s 299.068us 1 1 100.00
lc_ctrl_sec_cm 6.810s 253.946us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.670s 299.068us 1 1 100.00
lc_ctrl_sec_cm 6.810s 253.946us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.670s 299.068us 1 1 100.00
lc_ctrl_sec_cm 6.810s 253.946us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 9.300s 446.740us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.140s 549.244us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.200s 1255.351us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.760s 346.904us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.760s 346.904us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.540s 2125.266us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.470s 846.736us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.470s 846.736us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 36.550s 8202.821us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_errors 484495782689367585286409392773080241695407224421757722940116119184802894859 1496
UVM_INFO @ 317982641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [lc_ctrl_common_vseq] wait timeout occurred! 1 test run
lc_ctrl_csr_mem_rw_with_rand_reset 112131847363925905927634882208524740717209989601685462907583089133547057801527 96
UVM_INFO @ 10049999876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---