Simulation Results: lc_ctrl/volatile_unlock_enabled

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.77 %
  • code
  • 83.98 %
  • assert
  • 94.97 %
  • func
  • 93.37 %
  • line
  • 97.04 %
  • branch
  • 93.29 %
  • cond
  • 79.28 %
  • toggle
  • 86.72 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.230s 53.296us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.020s 29.696us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.080s 19.756us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.730s 225.170us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.600s 39.408us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.680s 101.663us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.080s 19.756us 1 1 100.00
lc_ctrl_csr_aliasing 1.600s 39.408us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.770s 341.813us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.370s 197.149us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.040s 100.350us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.050s 47.217us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.940s 173.292us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.420s 1347.971us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.940s 173.292us 1 1 100.00
lc_ctrl_prog_failure 2.050s 47.217us 1 1 100.00
lc_ctrl_errors 7.420s 1347.971us 1 1 100.00
lc_ctrl_security_escalation 4.460s 327.089us 1 1 100.00
lc_ctrl_jtag_state_failure 32.120s 2519.368us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.060s 292.120us 1 1 100.00
lc_ctrl_jtag_errors 25.760s 35104.398us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 6.810s 1104.465us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.900s 1202.232us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.060s 292.120us 1 1 100.00
lc_ctrl_jtag_errors 25.760s 35104.398us 1 1 100.00
lc_ctrl_jtag_access 2.790s 2729.123us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 14.440s 10151.953us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.580s 58.133us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.830s 159.397us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.100s 2468.435us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.610s 223.307us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.940s 154.348us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.420s 232.239us 1 1 100.00
lc_ctrl_jtag_alert_test 1.520s 157.376us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.750s 628.512us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.330s 94.378us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 39.410s 8534.390us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.150s 60.430us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.330s 204.363us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.330s 204.363us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.020s 29.696us 1 1 100.00
lc_ctrl_csr_rw 1.080s 19.756us 1 1 100.00
lc_ctrl_csr_aliasing 1.600s 39.408us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.090s 56.449us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.020s 29.696us 1 1 100.00
lc_ctrl_csr_rw 1.080s 19.756us 1 1 100.00
lc_ctrl_csr_aliasing 1.600s 39.408us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.090s 56.449us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.240s 1452.477us 1 1 100.00
lc_ctrl_tl_intg_err 1.910s 47.959us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.910s 47.959us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.370s 197.149us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.940s 173.292us 1 1 100.00
lc_ctrl_sec_cm 6.240s 1452.477us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.940s 173.292us 1 1 100.00
lc_ctrl_sec_cm 6.240s 1452.477us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.940s 173.292us 1 1 100.00
lc_ctrl_sec_cm 6.240s 1452.477us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.940s 173.292us 1 1 100.00
lc_ctrl_sec_cm 6.240s 1452.477us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.940s 173.292us 1 1 100.00
lc_ctrl_sec_cm 6.240s 1452.477us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.940s 173.292us 1 1 100.00
lc_ctrl_sec_cm 6.240s 1452.477us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.940s 173.292us 1 1 100.00
lc_ctrl_sec_cm 6.240s 1452.477us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.940s 173.292us 1 1 100.00
lc_ctrl_sec_cm 6.240s 1452.477us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.460s 327.089us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.770s 341.813us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.900s 1202.232us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.140s 1008.676us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.140s 1008.676us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.390s 5224.820us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.660s 2375.468us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.660s 2375.468us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 39.290s 11307.135us 1 1 100.00