Simulation Results: otbn

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.65 %
  • code
  • 86.22 %
  • assert
  • 90.00 %
  • func
  • 98.73 %
  • block
  • 99.23 %
  • line
  • 99.45 %
  • branch
  • 94.45 %
  • toggle
  • 84.76 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 15.000s 75.074us 1 1 100.00
otbn_smoke_vectorized 10.000s 59.509us 1 1 100.00
single_binary 1 1 100.00
otbn_single 11.000s 62.182us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 6.000s 28.356us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 98.340us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 6.000s 27.695us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 5.000s 268.073us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 8.000s 106.885us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 98.340us 1 1 100.00
otbn_csr_aliasing 5.000s 268.073us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 95.000s 2814.613us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 49.000s 2283.610us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 48.000s 115.872us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 90.000s 677.857us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 81.000s 394.984us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 98.000s 228.684us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 8.000s 238.991us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 8.000s 34.127us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 12.000s 34.959us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 6.000s 46.471us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 5.000s 40.182us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 8.000s 115.425us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 8.000s 115.425us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 6.000s 28.356us 1 1 100.00
otbn_csr_rw 5.000s 98.340us 1 1 100.00
otbn_csr_aliasing 5.000s 268.073us 1 1 100.00
otbn_same_csr_outstanding 6.000s 86.542us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 6.000s 28.356us 1 1 100.00
otbn_csr_rw 5.000s 98.340us 1 1 100.00
otbn_csr_aliasing 5.000s 268.073us 1 1 100.00
otbn_same_csr_outstanding 6.000s 86.542us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 10.000s 27.442us 1 1 100.00
otbn_dmem_err 10.000s 51.042us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 11.000s 970.790us 1 1 100.00
otbn_controller_ispr_rdata_err 10.000s 53.089us 1 1 100.00
otbn_mac_bignum_acc_err 11.000s 55.461us 1 1 100.00
otbn_urnd_err 7.000s 10.195us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 11.000s 59.545us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 8.000s 11.585us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 8.000s 15.221us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 735.000s 3240.710us 1 1 100.00
otbn_tl_intg_err 29.000s 125.108us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 67.000s 840.852us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 735.000s 3240.710us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 735.000s 3240.710us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 15.000s 75.074us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 10.000s 51.042us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 10.000s 27.442us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 29.000s 125.108us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 238.991us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 27.442us 1 1 100.00
otbn_dmem_err 10.000s 51.042us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 34.127us 1 1 100.00
otbn_illegal_mem_acc 11.000s 59.545us 1 1 100.00
otbn_sec_cm 735.000s 3240.710us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 735.000s 3240.710us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 11.000s 62.182us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 27.442us 1 1 100.00
otbn_dmem_err 10.000s 51.042us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 34.127us 1 1 100.00
otbn_illegal_mem_acc 11.000s 59.545us 1 1 100.00
otbn_sec_cm 735.000s 3240.710us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 735.000s 3240.710us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 238.991us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 27.442us 1 1 100.00
otbn_dmem_err 10.000s 51.042us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 34.127us 1 1 100.00
otbn_illegal_mem_acc 11.000s 59.545us 1 1 100.00
otbn_sec_cm 735.000s 3240.710us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 735.000s 3240.710us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 11.000s 62.182us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 9.000s 13.285us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 9.000s 24.863us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 40.000s 91.332us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 40.000s 91.332us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 10.000s 28.508us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 735.000s 3240.710us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 735.000s 3240.710us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 10.000s 51.716us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 735.000s 3240.710us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 735.000s 3240.710us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 9.000s 18.912us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 9.000s 18.912us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 8.000s 17.611us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 62.182us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 62.182us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 11.000s 62.182us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 81.000s 394.984us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 11.000s 62.182us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 11.000s 62.182us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 31.000s 484.400us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 11.000s 62.182us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 735.000s 3240.710us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 334.000s 4602.747us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1297) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 103091297315595476636140853019401504039356395820542855862748831485141677616520 325
UVM_INFO @ 4602747133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,196): Assertion NotRunningWhenLocked_A has failed 1 test run
otbn_urnd_err 73905061542649948231063559699150361497775315762113071797652826809339828910813 109
UVM_ERROR @ 10195392 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 10195392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---