Simulation Results: otp_ctrl

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 82.85 %
  • code
  • 79.67 %
  • assert
  • 94.83 %
  • func
  • 74.04 %
  • line
  • 88.77 %
  • branch
  • 84.49 %
  • cond
  • 92.67 %
  • toggle
  • 86.94 %
  • FSM
  • 45.49 %
Validation stages
V1
100.00%
V2
90.00%
V2S
88.89%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.020s 58.313us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 5.820s 2676.803us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.970s 185.098us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.280s 568.426us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 16.860s 5253.732us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.950s 421.746us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.600s 152.043us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.280s 568.426us 1 1 100.00
otp_ctrl_csr_aliasing 2.950s 421.746us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.630s 546.661us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.620s 49.488us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 14.630s 790.031us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.030s 146.279us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 9.960s 762.652us 1 1 100.00
otp_ctrl_check_fail 16.080s 874.724us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 6.310s 609.296us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 26.500s 14642.305us 1 1 100.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 4.060s 114.351us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 4.110s 474.858us 1 1 100.00
otp_ctrl_parallel_lc_esc 11.230s 1184.379us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 14.870s 899.472us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 58.220s 25251.384us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 5.450s 295.831us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 236.720s 56945.872us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.960s 63.061us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.380s 79.139us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.560s 61.744us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.560s 61.744us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.970s 185.098us 1 1 100.00
otp_ctrl_csr_rw 2.280s 568.426us 1 1 100.00
otp_ctrl_csr_aliasing 2.950s 421.746us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.570s 1127.931us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.970s 185.098us 1 1 100.00
otp_ctrl_csr_rw 2.280s 568.426us 1 1 100.00
otp_ctrl_csr_aliasing 2.950s 421.746us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.570s 1127.931us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
otp_ctrl_tl_intg_err 7.170s 1363.690us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 7.170s 1363.690us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 5.820s 2676.803us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 5.820s 2676.803us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 11.230s 1184.379us 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 11.230s 1184.379us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 11.230s 1184.379us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 11.230s 1184.379us 1 1 100.00
otp_ctrl_macro_errs 58.220s 25251.384us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 11.230s 1184.379us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 11.230s 1184.379us 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 11.230s 1184.379us 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 11.230s 1184.379us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 11.230s 1184.379us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 11.230s 1184.379us 1 1 100.00
otp_ctrl_macro_errs 58.220s 25251.384us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 11.230s 1184.379us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 11.230s 1184.379us 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.030s 146.279us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 16.080s 874.724us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 26.500s 14642.305us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 26.500s 14642.305us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 26.500s 14642.305us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 26.500s 14642.305us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 26.500s 14642.305us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 5.820s 2676.803us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 26.500s 14642.305us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 5.820s 2676.803us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 127.800s 21542.666us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 6.310s 609.296us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 5.820s 2676.803us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 5.820s 2676.803us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 58.220s 25251.384us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 13.110s 8095.129us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
otp_ctrl_stress_all_with_rand_reset 33.950s 17586.718us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 30815442009098817599558640944591695570100489161712441078986816664566006147874 9769
UVM_INFO @ 25251384141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1306) scoreboard [scoreboard] pwr_otp_idle output is * while expect * within * cycles 1 test run
otp_ctrl_parallel_key_req 107968258706707016989319494006107617209343799253676758412553024645777603159148 3127
UVM_INFO @ 114351267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---