Simulation Results: pwrmgr

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 95.77 %
  • code
  • 92.82 %
  • assert
  • 98.43 %
  • func
  • 96.05 %
  • line
  • 99.09 %
  • branch
  • 96.19 %
  • cond
  • 95.19 %
  • toggle
  • 99.62 %
  • FSM
  • 74.00 %
Validation stages
V1
83.33%
V2
93.33%
V2S
90.91%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.600s 24.530us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.760s 66.524us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.690s 16.000us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.560s 263.769us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.950s 151.855us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
pwrmgr_csr_mem_rw_with_rand_reset 3600.024s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.690s 16.000us 1 1 100.00
pwrmgr_csr_aliasing 0.950s 151.855us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 1.190s 124.899us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 1.190s 124.899us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.840s 701.010us 1 1 100.00
pwrmgr_lowpower_invalid 0.750s 45.142us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 0.670s 17.559us 1 1 100.00
pwrmgr_reset_invalid 0.690s 26.711us 0 1 0.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.670s 17.559us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.950s 69.205us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.700s 138.271us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.740s 93.110us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.670s 771.312us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.740s 19.605us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.830s 176.067us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.830s 176.067us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.760s 66.524us 1 1 100.00
pwrmgr_csr_rw 0.690s 16.000us 1 1 100.00
pwrmgr_csr_aliasing 0.950s 151.855us 1 1 100.00
pwrmgr_same_csr_outstanding 0.850s 53.484us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.760s 66.524us 1 1 100.00
pwrmgr_csr_rw 0.690s 16.000us 1 1 100.00
pwrmgr_csr_aliasing 0.950s 151.855us 1 1 100.00
pwrmgr_same_csr_outstanding 0.850s 53.484us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
pwrmgr_tl_intg_err 3600.026s 0.000us 0 1 0.00
pwrmgr_sec_cm 1.330s 318.020us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.330s 318.020us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.330s 318.020us 1 1 100.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 3600.026s 0.000us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.200s 997.884us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.950s 69.205us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.530s 1310.042us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.790s 51.156us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.710s 52.364us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.330s 318.020us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.330s 318.020us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.330s 318.020us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.660s 47.293us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.820s 35.337us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.600s 32.380us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.690s 16.000us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.690s 16.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.860s 730.949us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
pwrmgr_stress_all_with_rand_reset 3600.024s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 3 test runs
pwrmgr_tl_intg_err 104723096840558291268558333320007989957232522479655001983441414204595158696533 None
pwrmgr_stress_all_with_rand_reset 45878265731381285315415857472215162560308736487427549802014670752130779773396 None
pwrmgr_csr_mem_rw_with_rand_reset 14181428580364448745199700761622598125971655989616424845644879567345424237098 None
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 32935353453710090984900727989168272721018741750917631381823281333467644738015 85
UVM_ERROR @ 730949050 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 730949050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitDisClks 1 test run
pwrmgr_reset_invalid 27881493824066086095941717770488712178833471204915434529240101941146396165181 86
UVM_INFO @ 26711197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---