Simulation Results: rom_ctrl/192kb

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 97.18 %
  • code
  • 96.94 %
  • assert
  • 97.24 %
  • func
  • 97.36 %
  • line
  • 99.08 %
  • branch
  • 98.92 %
  • cond
  • 98.37 %
  • toggle
  • 95.00 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 22.390s 1035.952us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 28.730s 86.512us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 10.410s 61.182us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 12.180s 75.578us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 10.170s 121.723us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 11.170s 61.543us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 10.410s 61.182us 1 1 100.00
rom_ctrl_csr_aliasing 10.170s 121.723us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 10.340s 59.901us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 10.390s 54.287us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 14.470s 12.516us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 44.040s 194.488us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 34.690s 2256.138us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 12.650s 76.882us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 19.350s 2012.408us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 19.350s 2012.408us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 28.730s 86.512us 1 1 100.00
rom_ctrl_csr_rw 10.410s 61.182us 1 1 100.00
rom_ctrl_csr_aliasing 10.170s 121.723us 1 1 100.00
rom_ctrl_same_csr_outstanding 15.170s 75.947us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 28.730s 86.512us 1 1 100.00
rom_ctrl_csr_rw 10.410s 61.182us 1 1 100.00
rom_ctrl_csr_aliasing 10.170s 121.723us 1 1 100.00
rom_ctrl_same_csr_outstanding 15.170s 75.947us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 484.680s 46059.241us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 40.040s 160.120us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 857.260s 272.035us 1 1 100.00
rom_ctrl_tl_intg_err 190.750s 234.231us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 857.260s 272.035us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 857.260s 272.035us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 484.680s 46059.241us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 484.680s 46059.241us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 484.680s 46059.241us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 484.680s 46059.241us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 484.680s 46059.241us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 857.260s 272.035us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 857.260s 272.035us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 22.390s 1035.952us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 22.390s 1035.952us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 22.390s 1035.952us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 190.750s 234.231us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 484.680s 46059.241us 1 1 100.00
rom_ctrl_kmac_err_chk 34.690s 2256.138us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 484.680s 46059.241us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 484.680s 46059.241us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 484.680s 46059.241us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 40.040s 160.120us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 857.260s 272.035us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 79.610s 53987.054us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 10858346942177693253138470894883303408369702003656893326592718930021937234814 85
UVM_INFO @ 12516282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---