Simulation Results: rstmgr

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 97.43 %
  • code
  • 99.34 %
  • assert
  • 98.66 %
  • func
  • 94.28 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.68 %
  • toggle
  • 99.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.320s 268.656us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.190s 150.784us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.900s 72.273us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 7.790s 2470.685us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.770s 397.156us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.950s 105.068us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.900s 72.273us 1 1 100.00
rstmgr_csr_aliasing 2.770s 397.156us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.930s 91.948us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.620s 592.651us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.390s 247.864us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.400s 922.089us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.400s 922.089us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.400s 922.089us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.400s 922.089us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 20.940s 7408.875us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.020s 79.525us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.480s 132.122us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.480s 132.122us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.190s 150.784us 1 1 100.00
rstmgr_csr_rw 0.900s 72.273us 1 1 100.00
rstmgr_csr_aliasing 2.770s 397.156us 1 1 100.00
rstmgr_same_csr_outstanding 1.030s 136.320us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.190s 150.784us 1 1 100.00
rstmgr_csr_rw 0.900s 72.273us 1 1 100.00
rstmgr_csr_aliasing 2.770s 397.156us 1 1 100.00
rstmgr_same_csr_outstanding 1.030s 136.320us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 11.800s 8572.680us 1 1 100.00
rstmgr_tl_intg_err 2.850s 985.742us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 11.800s 8572.680us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 11.800s 8572.680us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.850s 985.742us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.910s 112.874us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.890s 2550.127us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.670s 301.739us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 11.800s 8572.680us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.900s 72.273us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.900s 72.273us 1 1 100.00