Simulation Results: rv_timer

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 92.28 %
  • code
  • 94.66 %
  • assert
  • 97.77 %
  • func
  • 84.41 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.860s 916.389us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.620s 19.677us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.620s 54.383us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.010s 1251.052us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.650s 20.556us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.650s 203.517us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.620s 54.383us 1 1 100.00
rv_timer_csr_aliasing 0.650s 20.556us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 0.750s 168.395us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 1.230s 2579.371us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 2.320s 3504.577us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 2.320s 3504.577us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.050s 214.012us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.540s 46.854us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.630s 20.262us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.780s 1418.236us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.780s 1418.236us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.620s 19.677us 1 1 100.00
rv_timer_csr_rw 0.620s 54.383us 1 1 100.00
rv_timer_csr_aliasing 0.650s 20.556us 1 1 100.00
rv_timer_same_csr_outstanding 0.720s 166.432us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.620s 19.677us 1 1 100.00
rv_timer_csr_rw 0.620s 54.383us 1 1 100.00
rv_timer_csr_aliasing 0.650s 20.556us 1 1 100.00
rv_timer_same_csr_outstanding 0.720s 166.432us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.760s 68.131us 1 1 100.00
rv_timer_tl_intg_err 1.010s 107.166us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.010s 107.166us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.580s 73.329us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.770s 846.564us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 7.040s 1235.094us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:179) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 40406220000193010391441266145335181579775723016649067971916443577093066587409 81
UVM_INFO @ 73328919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:342) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 1 test run
rv_timer_max 69292057679245399011875269922379454747129828472598801210689794644332390129055 81
UVM_INFO @ 846564327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---