Simulation Results: spi_device/1r1w

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 87.96 %
  • code
  • 91.39 %
  • assert
  • 95.27 %
  • func
  • 77.23 %
  • line
  • 98.89 %
  • branch
  • 98.22 %
  • cond
  • 96.16 %
  • toggle
  • 74.30 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 222.370s 155112.976us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.040s 163.783us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.440s 313.700us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 15.460s 2162.966us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 15.580s 1183.626us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.330s 390.500us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.440s 313.700us 1 1 100.00
spi_device_csr_aliasing 15.580s 1183.626us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.660s 11.751us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.120s 59.767us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.690s 13.569us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.870s 1.137us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.710s 3.998us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.040s 177.924us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.040s 177.924us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 6.960s 3223.871us 1 1 100.00
spi_device_tpm_sts_read 1.060s 50.673us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 9.910s 1583.156us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 5.170s 1934.015us 1 1 100.00
spi_device_flash_all 27.440s 27753.526us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 12.920s 8181.040us 1 1 100.00
spi_device_flash_all 27.440s 27753.526us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 12.920s 8181.040us 1 1 100.00
spi_device_flash_all 27.440s 27753.526us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 27.440s 27753.526us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 4.500s 1591.785us 1 1 100.00
spi_device_flash_all 27.440s 27753.526us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 4.500s 1591.785us 1 1 100.00
spi_device_flash_all 27.440s 27753.526us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 4.500s 1591.785us 1 1 100.00
spi_device_flash_all 27.440s 27753.526us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 4.500s 1591.785us 1 1 100.00
spi_device_flash_all 27.440s 27753.526us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 4.500s 1591.785us 1 1 100.00
spi_device_flash_all 27.440s 27753.526us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.360s 1221.982us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 4.260s 1444.996us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 4.260s 1444.996us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 4.260s 1444.996us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 13.240s 10261.510us 1 1 100.00
spi_device_read_buffer_direct 2.730s 1323.637us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 4.260s 1444.996us 1 1 100.00
spi_device_flash_all 27.440s 27753.526us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 27.440s 27753.526us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 27.440s 27753.526us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 6.120s 3924.187us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 6.120s 3924.187us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 52.960s 13570.811us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 222.370s 155112.976us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 18.620s 8834.464us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 132.870s 24485.118us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.660s 13.043us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.720s 11.928us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.090s 102.484us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.090s 102.484us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.040s 163.783us 1 1 100.00
spi_device_csr_rw 1.440s 313.700us 1 1 100.00
spi_device_csr_aliasing 15.580s 1183.626us 1 1 100.00
spi_device_same_csr_outstanding 2.850s 134.292us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.040s 163.783us 1 1 100.00
spi_device_csr_rw 1.440s 313.700us 1 1 100.00
spi_device_csr_aliasing 15.580s 1183.626us 1 1 100.00
spi_device_same_csr_outstanding 2.850s 134.292us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.030s 401.152us 1 1 100.00
spi_device_tl_intg_err 6.250s 205.729us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 6.250s 205.729us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1661) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 69092571538042117032077319289805431855904533962301220912409325920629844957453 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 807489 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 807489 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[947])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 50414948548234005719838735094903317068410671950793220638652420316920235810036 76
UVM_ERROR @ 1684401 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd [1101] vs 0x0 [0])
UVM_ERROR @ 1777401 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3e6 [1111100110] vs 0x0 [0])
UVM_ERROR @ 1778401 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4d [1001101] vs 0x0 [0])
UVM_ERROR @ 1792401 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x248 [1001001000] vs 0x0 [0])