Simulation Results: spi_host

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.64 %
  • code
  • 91.30 %
  • assert
  • 94.14 %
  • func
  • 89.50 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 2.000s 216.357us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 9.000s 41.795us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 9.000s 18.140us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 10.000s 256.878us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 9.000s 184.067us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 9.000s 60.987us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 9.000s 18.140us 1 1 100.00
spi_host_csr_aliasing 9.000s 184.067us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 9.000s 53.857us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 9.000s 67.332us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 9.000s 40.591us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 9.000s 137.592us 1 1 100.00
spi_host_error_cmd 9.000s 18.676us 1 1 100.00
spi_host_event 22.000s 7438.502us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 412.240us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 412.240us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 412.240us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 107.000s 7299.604us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 3.000s 127.574us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 9.000s 72.853us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 412.240us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 412.240us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 2.000s 216.357us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 2.000s 216.357us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 19.000s 4282.263us 1 1 100.00
spien 1 1 100.00
spi_host_spien 2.000s 1601.661us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 80.000s 3096.514us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 9.000s 84.897us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 9.000s 137.592us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 9.000s 27.697us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 9.000s 36.337us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 1.000s 250.247us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 1.000s 250.247us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 9.000s 41.795us 1 1 100.00
spi_host_csr_rw 9.000s 18.140us 1 1 100.00
spi_host_csr_aliasing 9.000s 184.067us 1 1 100.00
spi_host_same_csr_outstanding 9.000s 28.590us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 9.000s 41.795us 1 1 100.00
spi_host_csr_rw 9.000s 18.140us 1 1 100.00
spi_host_csr_aliasing 9.000s 184.067us 1 1 100.00
spi_host_same_csr_outstanding 9.000s 28.590us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 1614.246us 1 1 100.00
spi_host_sec_cm 1.000s 385.865us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 1614.246us 1 1 100.00