Simulation Results: sram_ctrl/main

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 94.87 %
  • code
  • 93.72 %
  • assert
  • 97.69 %
  • func
  • 93.20 %
  • block
  • 92.73 %
  • line
  • 93.64 %
  • branch
  • 89.45 %
  • toggle
  • 91.79 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 7.000s 718.770us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 42.504us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 16.253us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 39.896us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 14.486us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 349.910us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 16.253us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 14.486us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 251.000s 9228.949us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 163.000s 22965.027us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 28.000s 4799.059us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 212.000s 9542.444us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 172.000s 8713.463us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 39.000s 10882.408us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 38.000s 31761.794us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 15.000s 4773.600us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 784.481us 1 1 100.00
sram_ctrl_partial_access_b2b 249.000s 29319.150us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 7.000s 2653.687us 1 1 100.00
sram_ctrl_throughput_w_partial_write 6.000s 1340.387us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 2801.553us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 874.994us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 5.000s 1983.847us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 258.000s 47671.701us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 35.226us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 1113.063us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 1113.063us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 42.504us 1 1 100.00
sram_ctrl_csr_rw 2.000s 16.253us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 14.486us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 16.546us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 42.504us 1 1 100.00
sram_ctrl_csr_rw 2.000s 16.253us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 14.486us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 16.546us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 27.000s 14403.901us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 720.815us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 420.850us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 720.815us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 420.850us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 874.994us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 874.994us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 16.253us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 15.000s 4773.600us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 15.000s 4773.600us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 15.000s 4773.600us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 38.000s 31761.794us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 27.000s 14403.901us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 7.000s 718.770us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 7.000s 718.770us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 15.000s 4773.600us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 720.815us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 38.000s 31761.794us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 720.815us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 720.815us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 7.000s 718.770us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 720.815us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 12.000s 885.245us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 20450955553097559823172493055334789797884384615770665140949280892153916580705 None
sram_ctrl_mubi_enc_err 93526180825602919896812682953669519739364212198104047534352379371595602281913 None