Simulation Results: sysrst_ctrl

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 84.42 %
  • code
  • 91.41 %
  • assert
  • 91.19 %
  • func
  • 70.65 %
  • line
  • 96.33 %
  • branch
  • 96.63 %
  • cond
  • 94.23 %
  • toggle
  • 100.00 %
  • FSM
  • 69.87 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.800s 2122.273us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 4.540s 2455.409us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 4.580s 2406.582us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.940s 2566.177us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 10.650s 6016.461us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.620s 2072.979us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 49.780s 31820.743us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 5.140s 2935.917us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.840s 2191.021us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.620s 2072.979us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.140s 2935.917us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 62.620s 73304.222us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 153.790s 85389.171us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 2.210s 3661.124us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 7.560s 4278.859us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.860s 2538.724us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.650s 2144.211us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.300s 3809.911us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 4.980s 2614.617us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 1.780s 9215.853us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 52.470s 30455.402us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 71.390s 221793.810us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 4.490s 2014.507us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 4.030s 2015.276us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.460s 2308.248us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.460s 2308.248us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 10.650s 6016.461us 1 1 100.00
sysrst_ctrl_csr_rw 1.620s 2072.979us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.140s 2935.917us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 11.140s 4623.181us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 10.650s 6016.461us 1 1 100.00
sysrst_ctrl_csr_rw 1.620s 2072.979us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.140s 2935.917us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 11.140s 4623.181us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 41.570s 22010.237us 1 1 100.00
sysrst_ctrl_tl_intg_err 6.580s 22951.060us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 6.580s 22951.060us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 9.850s 11108.509us 1 1 100.00