Simulation Results: uart

 
24/08/2026 15:30:30 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 81.10 %
  • code
  • 90.99 %
  • assert
  • 98.56 %
  • func
  • 53.74 %
  • line
  • 98.86 %
  • branch
  • 96.50 %
  • cond
  • 93.93 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 0.900s 106.557us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.610s 27.666us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.580s 33.359us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.970s 285.303us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.850s 116.771us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.820s 70.662us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.580s 33.359us 1 1 100.00
uart_csr_aliasing 0.850s 116.771us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 34.560s 43358.252us 1 1 100.00
parity 2 2 100.00
uart_smoke 0.900s 106.557us 1 1 100.00
uart_tx_rx 34.560s 43358.252us 1 1 100.00
parity_error 2 2 100.00
uart_intr 26.180s 84683.483us 1 1 100.00
uart_rx_parity_err 28.010s 115005.051us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 34.560s 43358.252us 1 1 100.00
uart_intr 26.180s 84683.483us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 27.400s 57444.339us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 49.840s 76991.069us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 29.260s 37251.444us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 26.180s 84683.483us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 26.180s 84683.483us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 26.180s 84683.483us 1 1 100.00
perf 1 1 100.00
uart_perf 114.700s 18531.232us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.900s 3142.371us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.900s 3142.371us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 1.630s 3437.645us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 6.810s 30945.113us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.410s 1364.181us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 2.770s 2348.392us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 341.140s 98204.741us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 15.430s 11627.852us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.610s 42.396us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.650s 46.788us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.410s 63.093us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.410s 63.093us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.610s 27.666us 1 1 100.00
uart_csr_rw 0.580s 33.359us 1 1 100.00
uart_csr_aliasing 0.850s 116.771us 1 1 100.00
uart_same_csr_outstanding 0.750s 116.758us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.610s 27.666us 1 1 100.00
uart_csr_rw 0.580s 33.359us 1 1 100.00
uart_csr_aliasing 0.850s 116.771us 1 1 100.00
uart_same_csr_outstanding 0.750s 116.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.770s 134.682us 1 1 100.00
uart_tl_intg_err 1.160s 319.973us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.160s 319.973us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 24.300s 3209.872us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr 1 test run
uart_noise_filter 68586504982847907796931590497226299089655535523862136414096415686447140591847 80
UVM_ERROR @ 421532919 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_ERROR @ 479793439 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 479880395 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 480184741 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 251 [0xfb]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:390) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_stress_all 83689106249461793220238376432467007686302211775212246181630326112059110455572 87
UVM_ERROR @ 11239682293 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 11253937213 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 11402837299 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 11402837299 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr